A built-in testable architecture and design method for on-chip error correction circuits of embedded memories in VLSI/ASIC systems

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dc.contributor.authorCui, Lianfaen_US
dc.date.accessioned2013-03-19T20:31:23Z
dc.date.available2013-03-19T20:31:23Z
dc.date.issued1994en_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstracten_US
dc.format.extentvii, 89, [60] leaves :en_US
dc.identifierocm00127668en_US
dc.identifier.urihttp://hdl.handle.net/1993/17890
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleA built-in testable architecture and design method for on-chip error correction circuits of embedded memories in VLSI/ASIC systemsen_US
dc.typemaster thesisen_US
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