The simulation and its verification of high-speed printed circuit boards with CAD/CAE tools
dc.contributor.author | Zarychta, Jaroslaw | en_US |
dc.date.accessioned | 2013-03-04T21:47:31Z | |
dc.date.available | 2013-03-04T21:47:31Z | |
dc.date.issued | 1989 | en_US |
dc.degree.discipline | Electrical Engineering | en_US |
dc.degree.level | Master of Science (M.Sc.) | en_US |
dc.description.abstract | en_US | |
dc.format.extent | xii, 149 leaves : | en_US |
dc.identifier | ocm72746898 | en_US |
dc.identifier.uri | http://hdl.handle.net/1993/16938 | |
dc.language.iso | eng | en_US |
dc.rights | open access | en_US |
dc.title | The simulation and its verification of high-speed printed circuit boards with CAD/CAE tools | en_US |
dc.type | master thesis | en_US |
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