Improved HVdc dynamic performace via phase locking to virtual Thévenin voltage
Abstract
An impedance-compensated phase-locked loop (IC-PLL) that synchronizes the
input signal to a virtual estimate of ac network Thévenin equivalent voltage is
introduced and evaluated for application in HVdc systems. As compared with
the conventional Trans-vector PLL method, it is shown that the enhanced
tracking ability of the IC-PLL improves the dynamic performance of the HVdc
system. The thesis shows that these benefits accrue in LCC-HVdc systems as
well as VSC-HVdc systems.
In the LCC-HVdc system, a frequency scan of the system shows the use of
the IC-PLL reduces the effective resonant impedance of the system, and therefore
increases system’s immunity to the harmonic instability at low order frequencies.
In the VSC-HVdc system, the robust tracking performance of the ICPLL
reduces the system’s sensitivity to the PLL gains, and strengthens the stable
operation following disturbances. The impact of the IC-PLL parameters in
the VSC-HVdc system is evaluated by a validated small signal model. The eigenvalue
based analysis shows that the stability of the system, is no longer
greatly impacted by the ac system strength with the implementation of the ICPLL.
Unlike the Trans-vector PLL based system, it shows that a VSC-HVdc
system operating at low SCR with high PLL gains is stable.
Description
Keywords
HVdc system, Phase-locked loop