Improved HVdc dynamic performace via phase locking to virtual Thévenin voltage
| dc.contributor.author | Ajinai | |
| dc.contributor.examiningcommittee | Annakkage, Udaya (Electrical and Computer Engineering) Jacobson, David (Electrical and Computer Engineering) Yuan, Quiyan (Civil Engineering) | en_US |
| dc.contributor.supervisor | Gole, Aniruddha (Electrical and Computer Engineering) | en_US |
| dc.date.accessioned | 2017-06-21T14:12:49Z | |
| dc.date.available | 2017-06-21T14:12:49Z | |
| dc.date.issued | 2017 | |
| dc.degree.discipline | Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Science (M.Sc.) | en_US |
| dc.description.abstract | An impedance-compensated phase-locked loop (IC-PLL) that synchronizes the input signal to a virtual estimate of ac network Thévenin equivalent voltage is introduced and evaluated for application in HVdc systems. As compared with the conventional Trans-vector PLL method, it is shown that the enhanced tracking ability of the IC-PLL improves the dynamic performance of the HVdc system. The thesis shows that these benefits accrue in LCC-HVdc systems as well as VSC-HVdc systems. In the LCC-HVdc system, a frequency scan of the system shows the use of the IC-PLL reduces the effective resonant impedance of the system, and therefore increases system’s immunity to the harmonic instability at low order frequencies. In the VSC-HVdc system, the robust tracking performance of the ICPLL reduces the system’s sensitivity to the PLL gains, and strengthens the stable operation following disturbances. The impact of the IC-PLL parameters in the VSC-HVdc system is evaluated by a validated small signal model. The eigenvalue based analysis shows that the stability of the system, is no longer greatly impacted by the ac system strength with the implementation of the ICPLL. Unlike the Trans-vector PLL based system, it shows that a VSC-HVdc system operating at low SCR with high PLL gains is stable. | en_US |
| dc.description.note | October 2017 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1993/32268 | |
| dc.language.iso | eng | en_US |
| dc.rights | open access | en_US |
| dc.subject | HVdc system, Phase-locked loop | en_US |
| dc.title | Improved HVdc dynamic performace via phase locking to virtual Thévenin voltage | en_US |
| dc.type | master thesis | en_US |