Fault counting and design of fault-tolerant reconfigurable hierarchical interconnection networks for linear WSI arrays using status logic
| dc.contributor.author | Sul, Chinsong. | en_US |
| dc.date.accessioned | 2013-04-08T16:54:38Z | |
| dc.date.available | 2013-04-08T16:54:38Z | |
| dc.date.issued | 1992 | en_US |
| dc.identifier | ocm00011297 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1993/18670 | |
| dc.description.abstract | en_US | |
| dc.format.extent | viii, 54 leaves : | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | open access | en_US |
| dc.title | Fault counting and design of fault-tolerant reconfigurable hierarchical interconnection networks for linear WSI arrays using status logic | en_US |
| dc.type | master thesis | en_US |
| dc.degree.discipline | Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Science (M.Sc.) | en_US |
