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dc.contributor.authorSul, Chinsong.en_US
dc.date.accessioned2013-04-08T16:54:38Z
dc.date.available2013-04-08T16:54:38Z
dc.date.issued1992en_US
dc.identifierocm00011297en_US
dc.identifier.urihttp://hdl.handle.net/1993/18670
dc.description.abstracten_US
dc.format.extentviii, 54 leaves :en_US
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleFault counting and design of fault-tolerant reconfigurable hierarchical interconnection networks for linear WSI arrays using status logicen_US
dc.typemaster thesisen_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US


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