Fault counting and design of fault-tolerant reconfigurable hierarchical interconnection networks for linear WSI arrays using status logic

Simple item page
dc.contributor.authorSul, Chinsong.en_US
dc.date.accessioned2013-04-08T16:54:38Z
dc.date.available2013-04-08T16:54:38Z
dc.date.issued1992en_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstracten_US
dc.format.extentviii, 54 leaves :en_US
dc.identifierocm00011297en_US
dc.identifier.urihttp://hdl.handle.net/1993/18670
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleFault counting and design of fault-tolerant reconfigurable hierarchical interconnection networks for linear WSI arrays using status logicen_US
dc.typemaster thesisen_US
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
Sul_Fault_counting.pdf
Size:
2.7 MB
Format:
Adobe Portable Document Format
Description:
Download
Collections
FGS - Electronic Theses and Practica