Adaptive Phase Locked Loops for VSC connected to weak ac systems
dc.contributor.author | Babu Narayanan, Mita | |
dc.contributor.examiningcommittee | Zhang, Yi (Electrical and Computer Engineering) Leung, Carson (Computer Science) | en_US |
dc.contributor.supervisor | Gole, Aniruddha (Electrical and Computer Engineering) | en_US |
dc.date.accessioned | 2015-04-13T16:16:59Z | |
dc.date.available | 2015-04-13T16:16:59Z | |
dc.date.issued | 2015-04-13 | |
dc.degree.discipline | Electrical and Computer Engineering | en_US |
dc.degree.level | Master of Science (M.Sc.) | en_US |
dc.description.abstract | The performance of the High voltage dc systems is dependent on the stiffness of the ac bus, it is connected to. With the traditional synchronous reference frame-phase locked loops (SRF-PLL), voltage source converters (VSC) systems with large PLL gains, connected to weak ac networks are shown to be prone to instabilities, when subject to disturbances. In this thesis a new Adaptive PLL is designed with a pre-filter topology which extracts the fundamental positive sequence component of the input voltage, to be fed into the SRF-PLL for tracking of its phase angle. Compared with other traditional PLL topologies, this Adaptive PLL shows superior immunity to voltage distortions, and also has a faster dynamic performance. The thesis presents a comparative analysis of the performance of the traditional SRF-PLL with the Adaptive PLL in a VSC control system, and its impact on stability for VSCs connected to weak ac systems (up to SCR=1.3). | en_US |
dc.description.note | October 2015 | en_US |
dc.identifier.uri | http://hdl.handle.net/1993/30385 | |
dc.language.iso | eng | en_US |
dc.rights | open access | en_US |
dc.subject | Voltage Source Converters | en_US |
dc.subject | High Voltage DC systems | en_US |
dc.subject | Phase Locked Loops | en_US |
dc.subject | Short Circuit Ratio | en_US |
dc.title | Adaptive Phase Locked Loops for VSC connected to weak ac systems | en_US |
dc.type | master thesis | en_US |