VLSI implementation of a digital neural network with on-chip learning

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dc.contributor.authorGates, Darrellen_US
dc.date.accessioned2013-03-04T21:56:42Z
dc.date.available2013-03-04T21:56:42Z
dc.date.issued1990en_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstractThis thesis explores the VLSI implementation of a neural network with on-chip learning capabilities. This digital ASIC is intended to be used as the basis for a high-speed neural accelerator board. A unique digital neural network architecture is presented and analyzed. A novel VLSI design style is introduced and developed. Implementation details and design issues are also presented. Fundamental issues of neural networks are introduced and major learning paradigms are discussed. A thorough examination of digital ANNs is presented.en_US
dc.format.extentix, 106 leaves :en_US
dc.identifierocm72779126en_US
dc.identifier.urihttp://hdl.handle.net/1993/17026
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleVLSI implementation of a digital neural network with on-chip learningen_US
dc.typemaster thesisen_US
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