High-speed Viterbi decoder design and implementation with FPGA
| dc.contributor.author | Lin, Jian | en_US |
| dc.date.accessioned | 2007-05-22T15:12:44Z | |
| dc.date.available | 2007-05-22T15:12:44Z | |
| dc.date.issued | 2000-12-01T00:00:00Z | en_US |
| dc.degree.discipline | Electrical and Computer Engineering | en_US |
| dc.degree.level | Master of Science (M.Sc.) | en_US |
| dc.description.abstract | This thesis describes a design and implementation of a Viterbi decoder using FPGA technology. We use the sliding block filtering concept, the pipeline interleaving technique and the forward processing method to construct the design. We use VHDL to describe the design, Synopsys tools to synthesize it and Xilinx tools to target the design to an XVC300-8 device. Besides the above, the principle of the Viterbi Algorithm, two kinds of structures of the Viterbi decoder, VHDL coding style, a high level synthesis strategy and the methodologies of FPGA design are briefly discussed. We also present complete source code, scripts and reports for this design in appendixes. | en_US |
| dc.format.extent | 4873331 bytes | |
| dc.format.extent | 184 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.format.mimetype | text/plain | |
| dc.identifier.uri | http://hdl.handle.net/1993/2007 | |
| dc.language.iso | eng | en_US |
| dc.rights | open access | en_US |
| dc.title | High-speed Viterbi decoder design and implementation with FPGA | en_US |
| dc.type | master thesis | en_US |