FPGA implementation of impedance-compensated phase-locked loop

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dc.contributor.authorYi, Yue
dc.contributor.examiningcommitteeZhou, Jenny (Electrical and Computer Engineering) Leung, Carson (Computer Science)en_US
dc.contributor.supervisorGole, Aniruddha (Electrical and Computer Engineering)en_US
dc.date.accessioned2019-02-26T22:29:39Z
dc.date.available2019-02-26T22:29:39Z
dc.date.issued2019-02-19en_US
dc.date.submitted2019-02-19T22:01:13Zen
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstractThe Phase-Locked Loop (PLL) plays a key role in HVdc systems. Recently, a new type of PLL called the Impedance-Compensated Phase-Locked Loop (IC-PLL) was introduced to compensate for the voltage drop across the ac network's Thevenin impedance, making the phase locking more robust against transients and harmonics. The IC-PLL has an improved dynamic response as compared with the traditional approaches. However, prior to this thesis, studies of the IC-PLL were based on off-line simulations. In this thesis, an actual IC-PLL is constructed in hardware using a Field- Programmable Gate Array(FPGA). Paralleled structure is implemented on the FPGA to achieve high speed. The IC-PLL's performance is investigated by connecting it to a real-time model of the HVdc system simulated using a Real-Time Digital Simulator (RTDS). Different types of system disturbances such as sudden step change in power, voltage magnitude change and voltage distortion are applied to examine the IC- PLL's dynamic behaviour. Results are compared with the traditional Trans-vector PLL (TV-PLL). The results show the IC-PLL tracks the phase and frequency of the Point of Common Coupling(PCC) voltage in the steady-state and has a minimal error with load changes. Moreover, this thesis investigated potential sources of error when conducting the Controller Hardware-in-Loop (CHIL) simulation of the IC-PLL. The investigation was carried out by building a detailed off-line simulation of the CHIL simulation itself by including models of the interface delays, offsets and finite precision of ADC and DACs. The results show that for this type of interfacing, the constant interface delay and offsets have minimal impact on the accuracy, however, finite precision of ADC and DACs will have a significant impact on the CHIL simulation.en_US
dc.description.noteMay 2019en_US
dc.identifier.citationY. Yi, Ajinai and A.M. Gole, “FPGA Implementation of Impedance-Compensated Phase-Locked Loop for HVdc Converters,” The Journal of Engineering, 2018, DOI: 10.1049/joe.2018.8789, IET Digital Libraryen_US
dc.identifier.citationY. Yi, A.D. Sinkar and A.M. Gole, “Effects of Time Delay, DC Offset and Truncation Errors on Interfacing of a Phase-Locked Loop (PLL) with a Real-time Simulator for Controller Hardware-In-the-Loop(CHIL) Simulation” The 15th IET International Conference on AC and DC Power Transmission, 5-7 February 2019en_US
dc.identifier.urihttp://hdl.handle.net/1993/33764
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.subjectHVDCen_US
dc.subjectFPGAen_US
dc.subjectPhase-Locked Loopen_US
dc.subjectLCCen_US
dc.subjectHardware-In-the-Loopen_US
dc.titleFPGA implementation of impedance-compensated phase-locked loopen_US
dc.typemaster thesisen_US
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