Delay fault testing and statistical detectability analysis in scan-based logic circuits

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dc.contributor.authorZhang, Zaifuen_US
dc.date.accessioned2013-04-18T14:51:05Z
dc.date.available2013-04-18T14:51:05Z
dc.date.issued1995en_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelDoctor of Philosophy (Ph.D.)en_US
dc.description.abstracten_US
dc.format.extentxix, 170 leaves :en_US
dc.identifier(Sirsi) AJA-3705en_US
dc.identifier.urihttp://hdl.handle.net/1993/19057
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleDelay fault testing and statistical detectability analysis in scan-based logic circuitsen_US
dc.typedoctoral thesisen_US
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