The method of selective harmonic elimination is often used as an efficient means for obtaining harmonic-reduced waveforms from voltage sourced converters (VSC). However, the switching angles required for its implementation are usually pre-calculated on the basis of a fixed dc bus voltage. In practice, there are harmonies present in the dc source because of the finite dc bus capacitance and other realistic operating conditions, which can potentially introduce additional noncharacteristic harmonics. This paper examines the harmonic performance of a VSC-based static synchronous compensator as a function of design and operating parameters. These include the value of dc capacitor, the strength of the connected ac network and ac system unbalance. The results are generated using theoretical analysis for special cases and numerical simulation using electromagnetic transients simulation for the more general case.