The simulation of variable time delay using a process computer (IBM System/7)

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dc.contributor.authorChakrabarty, Dibendu Nathen_US
dc.date.accessioned2012-12-14T19:40:52Z
dc.date.available2012-12-14T19:40:52Z
dc.date.issued1974en_US
dc.degree.disciplineElectrical Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstracten_US
dc.format.extentvi, 42 leaves.en_US
dc.identifierocm72756876en_US
dc.identifier.urihttp://hdl.handle.net/1993/13399
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleThe simulation of variable time delay using a process computer (IBM System/7)en_US
dc.typemaster thesisen_US
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