High level design and test methodologies with VHDL

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dc.contributor.authorWang, Ruomeien_US
dc.date.accessioned2013-04-19T20:11:35Z
dc.date.available2013-04-19T20:11:35Z
dc.date.issued1996en_US
dc.degree.disciplineElectrical and Computer Engineeringen_US
dc.degree.levelMaster of Science (M.Sc.)en_US
dc.description.abstracten_US
dc.format.extentix, 105 leaves :en_US
dc.identifier(Sirsi) AJP-9891en_US
dc.identifier.urihttp://hdl.handle.net/1993/19366
dc.language.isoengen_US
dc.rightsopen accessen_US
dc.titleHigh level design and test methodologies with VHDLen_US
dc.typemaster thesisen_US
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