Show simple item record

dc.contributor.supervisor Filizadeh, Shaahin (Electrical & Computer Engineering) en_US
dc.contributor.author Espah Boroojeni, Mehrdad
dc.date.accessioned 2012-01-19T22:31:36Z
dc.date.available 2012-01-19T22:31:36Z
dc.date.issued 2012-01-19
dc.identifier.uri http://hdl.handle.net/1993/5108
dc.description.abstract Multi-level converters that provide more than two levels of voltage to achieve an output waveform closer to sinusoidal waveform with less distortion are very attractive to power applications. This thesis investigates several multi-level converter topologies and different modulation strategies such as pulse-width modulation and space vector modulation. Attention is paid in particular to SVM strategy. Although SVM strategy is applicable for N-level converter, this thesis only focuses on five-level and three-level diode clamped converter (DCC). Despite their appealing harmonic spectrum and low losses, multi-level converters are known to suffer from inherent voltage imbalance on their dc side. The thesis presents a method in order to balance the dc side capacitor voltages for an N-level converter. The presented balancing method is based on minimizing a cost function which is related to voltage divergence of the dc capacitors. This method is used for a three-level SVM to overcome the voltage drifting problem. en_US
dc.rights info:eu-repo/semantics/openAccess
dc.subject Multi-level converters en_US
dc.title DC capacitor voltage balancing in multi-level converters en_US
dc.type info:eu-repo/semantics/masterThesis
dc.degree.discipline Electrical and Computer Engineering en_US
dc.contributor.examiningcommittee Fung, Wai-Keung (Electrical & Computer Engineering) Derksen, Robert (Mechanical Engineering) en_US
dc.degree.level Master of Science (M.Sc.) en_US
dc.description.note February 2012 en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

View Statistics