Research on stability issues of a grid-connected PV inverter in power hardware in the loop (PHIL) architecture
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This thesis presents an in-detail stability analysis of a Power Hardware in the Loop (PHIL) network formed through an Ideal Transformer Method (ITM) interface. The ever-growing demand for PHIL testing necessitates thorough research in the area. The ITM interface devices are crucial in determining the accurate and stable PHIL. Therefore, this thesis considers the parameters of these individual devices to develop analytical equations with which the stability can be determined quantitatively. This helps in choosing the interface devices as well as the system parameters before forming the PHIL setup. The PHIL testing is something that requires an experimental result to validate its operation besides the theoretical and mathematical formulations. The work in this thesis follows the methodology of mathematical analysis followed by experimental results. The PHIL setup used in this thesis for its analysis considers a simple resistor divider network to formulate its hypothesis and finally extends the study to evaluate a Grid-Connected PV Inverter (GCPI) in a PHIL architecture. The delay present in the PHIL network as a result of non-ideal interface devices creates a major discrepancy between the results in the actual system with the PHIL system. In order to eliminate the effect of this delay, this thesis considers the application of a Smith Predictor (SP) compensator. This SP compensator consists of a model of the interface and the estimation of the delay in the PHIL network of choice. This thesis works towards developing the model of the interface device in the ITM interface. To validate the model, an experimental gain and phase measurements are made and compared with the gain and phase of the model. This ensures that an accurate model of the interface is obtained to model the SP compensator. Also, the round-trip delay of the PHIL network under study is estimated through various combinations of I/O devices. Once the SP compensator model is developed, it is implemented in Real Time Digital Simulator (RTDS) to verify the stability predictions made from the theory. The SP employed PHIL network with resistor divider and a GCPI is used as actual hardware for the experimental validations. Besides the stability analysis of a PHIL network, this thesis also presents a fundamental work that could benefit the dynamic response of a switched-mode amplifier. The switched-mode amplifier with a conventional linear controller would have a bandwidth limited by the converter parameters. This thesis explores the area of non-linear control by implementing a Second Order Switching Surface (SSS) based Boundary Controller (BC) to a Full Bridge (FB) Voltage Source Inverter (VSI) operating with unipolar switching. The experiments are performed in a 550 VA, VSI prototype which showed a transient response in the range or 150-320 µs. This can easily be extended to push the dynamic response of such a setup with the use of an advanced digital control card complemented by a higher switching semiconductor device.