Magnetic force microscopy imaging of current paths in integrated circuits with overlayers
Imaging of current in internal conductors through magnetic field detection by magnetic force microscopy (MFM) is of growing interest in the analysis of integrated circuits (ICs). This thesis presents a systematic study of the MFM based mapping of current in model circuits by using force and force gradient techniques. In comparing these two techniques, force was found to have a much higher signal to noise ratio (from ~150 to ~580 times) than force gradient at large tip-sample distances considering the presence of thick overlayers in ICs. As a result, force will have better sensitivity and can therefore be used to detect much smaller minimum currents. We have achieved a sensitivity of ~0.64 µA per square-root Hertz in air and ~0.095 µA per squre-root Hertz in vacuum for force with a pinning field with a probe-circuit separation of 1.0 µm. We conclude that the force technique is superior for the application of MFM current imaging of buried conductors, albeit with reduced spatial resolution. Numerical modeling of the MFM images has shown that the simple point probe approximation is insufficient to model MFM images. An extended model, which considers realistic MFM probe geometries and the forces acting on the whole probe, has been shown to be necessary. Qualitative and quantitative comparisons of the experimental and simulation results with this model are in agreement to within experimental uncertainty. The comparisons suggested that the CoCr film thickness is not uniform on the probe, which was verified by scanning electron microscope cross-section images of the probes cut by a focused ion beam. Most notably, the CoCr film was 1.5 times thicker on the cantilever than on the tip. Based on the simulation and experimental results, we have devised a method to accurately locate the current path from MFM images with submicrometer uncertainty. The method was tested for different patterns of model conducting lines. It was shown to be a useful technique for fault location in IC failure analysis when current flows through the devices buried under overlayers and no topographic features are on the surface to provide clues about the positions of the devices.