The design principle and the data acquisition processing of a full-curve computerized deep-level transient spectroscopy (DLTS) system are described in detail. This system is more reliable, flexible and accurate than the conventional methods in the determination of deep level traps in semiconductor devices. The procedures for the evaluation of the bulk traps for p-n junctions and for the evaluation of both the bulk traps and interface states for MOS capacitors are fully discussed. For MOS capacitors, the analysis is based on the rate window concept. The method of minimizing the error in determining the trap energy levels from the transient capacitance spectra is given. We have used the MOS capacitors produced in our Materials and Devices Research Laboratory as an example to demonstrate how to use our new DLTS system to determine their trap parameters. It is found that there are two deep trap levels in the semiconductor bulk and that the interface states are distributed in the forbidden gap.