VLSI implementation of a digital neural network with on-chip learning

Gates, Darrell

VLSI implementation of a digital neural network with on-chip learning

Files

Gates_Darrell.pdf(6.17 MB)

Date

1990

Authors

Gates, Darrell

Abstract

This thesis explores the VLSI implementation of a neural network with on-chip learning capabilities. This digital ASIC is intended to be used as the basis for a high-speed neural accelerator board. A unique digital neural network architecture is presented and analyzed. A novel VLSI design style is introduced and developed. Implementation details and design issues are also presented. Fundamental issues of neural networks are introduced and major learning paradigms are discussed. A thorough examination of digital ANNs is presented.

URI

http://hdl.handle.net/1993/17026

Collections

FGS - Electronic Theses and Practica

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