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Faculty of Graduate Studies (Electronic Theses and Practica)
FGS - Electronic Theses and Practica
High speed sequential demodulator based on shift register systolic priority queue architecture
High speed sequential demodulator based on shift register systolic priority queue architecture
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Ng_High_speed.pdf
(4.28 MB)
Date
1993
Authors
Ng, Hoo Man
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URI
http://hdl.handle.net/1993/17773
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FGS - Electronic Theses and Practica
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