Non-invasive internal pattern extraction of integrated circuits using electrostatic force microscopy
Improvements in technology of the microelectronic areas have allowed researchers to develop Integrated Circuits (ICs) with higher speed and smaller size. However these improvements have also increased the difficulties for diagnostic testing of the circuits in the radio frequency (RF) range. The ideal measurement technique must be non-invasive with high spatial resolution, high temporal resolution, high sensitivity. It must be easy to use and cost effective. The current techniques do not meet the above combined criteria. This thesis introduces a simple non-contact technique, based on the Electrostatic Force Microscope (EFM), for internal testing of microelectronic circuits. A heterodyne technique which utilizes short electrical pulses for sampling is implemented to extract an arbitrary periodic digital pattern. This thesis also evaluates three narrow pulse generation techniques. An Integrated Circuit version of the Non-Linear Transmission Line (NLTL) was designed, fabricated and tested. Using the heterodyne technique, measurements of 0.5 Gb/s and 1 Gb/s are performed on 50 W transmission line as well as on internal nodes of BiCMOS and CMOS integrated circuits. Results show that the proposed technique is a capable tool for diagnostic testing of high frequency microelectronic circuits while satisfying the above requirements.