Show simple item record Chakrabarty, Dibendu Nath en_US 2012-12-14T19:40:52Z 2012-12-14T19:40:52Z 1974 en_US
dc.identifier ocm72756876 en_US
dc.description.abstract en_US
dc.format.extent vi, 42 leaves. en_US
dc.language en en_US
dc.rights en_US
dc.rights info:eu-repo/semantics/openAccess
dc.title The simulation of variable time delay using a process computer (IBM System/7) en_US
dc.type info:eu-repo/semantics/masterThesis
dc.type master thesis en_US Electrical Engineering en_US

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