'Laser Lock - Memory Address Controller.SXB
'-------------------------------------------------------------------------------------
'Overview:
'-------------------------------------------------------------------------------------

'The Memory Address Controller is responsible for the address bus of the M48Z02 NVRAM 
' chip.  This controller is hooked up to the CS and Miso lines of the serial bus, but 
' communicates handshaking through the Memory Data Controller.  The Memory Data 
' controller handles the read/write control of the M48Z02 NVRAM chip, as well as the
' serial data transfer to the main controller.


'-------------------------------------------------------------------------------------
'Notes
'-------------------------------------------------------------------------------------

'Inputs:
' Serial Input from Laser Lock main controller

'Outputs:
' Address bus to M48Z02 NVRAM
' Acknowledge line to Memory data Controller


'-------------------------------------------------------------------------------------
'Speed selection and device initialization
'-------------------------------------------------------------------------------------

DEVICE	SX28, OSC4MHZ, TURBO, STACKX, OPTIONX
'-using an SX28 device, with internal clock of 4 MHz
'-TURBO refers to the operation mode, where one clock cycle per
'instruction.
'-STACKX, OPTIONX required for SX28 only (apparently - P32 of Practical SXBasic 
' programming guide)
'when programming SX48, TURBO, STACKX, and OPTIONX are assumed

'this is used for timing-specific parts of the code, like PAUSE
'this is also used by the SX-KEY, as it generates a clock for debugging
'purposes
FREQ	4_000_000

'NOTE: the underscore can be used to separate number values to improve readability
'	eg binary valu %0100_0010  versus %01000010


'-------------------------------------------------------------------------------------
'Pin Assignment
'-------------------------------------------------------------------------------------

AddrBusLSB	PIN	RB	Output
AddrBusMSB	PIN	RC	Output

AddrReady	Pin	RA.1	Output		'Memory Address controller ready signal 
						' (active high)

CS	PIN	RA.2	Input
Mosi	PIN	RA.0	Input	'Master out, slave in - SPI input for this device

'attention acknowledge - special case:  this doesn't sit on the SPI bus, so it can hold 
' this as output
AttnAck	PIN	RA.3	Output

Debug	Pin	RC.7	Output


'-------------------------------------------------------------------------------------
'Variable Declaration
'-------------------------------------------------------------------------------------

'running indices for loops
i		var	byte
j		var 	byte

'packet data
packet	var	byte(10)


'-------------------------------------------------------------------------------------
'Subroutine Definitions
'-------------------------------------------------------------------------------------

'subroutine definitions
ASyncPacketRead		sub	0	'slave asynchronous serial packet read


'-------------------------------------------------------------------------------------
'Main Program
'-------------------------------------------------------------------------------------

'The PROGRAM directive specifies the label where the program begins.
'In this case, "Start" is the label specified.  This also specifies
'where to put the internally generated SX initialization code.
'NOTE: to manually remove the initialization code, look into
'the NOSTARTUP option for the PROGRAM directive
PROGRAM Start

'the Start label
Start:

'set all outputs appropriately
Low AddrReady
high AttnAck

pause 100
'TODO: POST the NVRAM?



'startup config: set the position to an intermediate spot

'main loop:
'---------

MainLoop:

'wait for next instruction from main controller
ASyncPacketRead

'respond to packet data
if packet(1) = $01 then		'command $01: read from specified address

	'set the address on the address bus
	AddrBusLSB = packet(2)
	AddrBusMSB = packet(3)
	
	'TODO: pause?  The M48Z02 needs about 70 ns to get ready
	pauseus 1

	'let the memory data controller know that the address is ready on the address 
	' bus
	high AddrReady

	'When the main controller is reading from an address, need to watch 
	' handshaking here to wait for the main controller's read transfer to finish.
	' That way this chip won't get stuck thinking the main controller is trying 
	' to write when really it is trying to read
	
	'wait for read handshaking to start
	do while CS = 1
	loop
	
	'wait for read handshaking to end
	do while CS = 0
	loop


elseif packet(1) = $02 then		'command $02: write to specified address

	'set the address on the address bus
	AddrBusLSB = packet(2)
	AddrBusMSB = packet(3)
	
	'TODO: pause?  The M48Z02 needs about 70 ns to get ready
	pauseus 1

	'let the memory data controller know that the address is ready on the address 
	' bus
	high AddrReady

elseif packet(1) = $AA then	'debug command $AA: display packet(2) on LSB

	AddrBusLSB = packet(2)	


endif


GOTO MainLoop


'-------------------------------------------------------------------------------------
'Subroutines
'-------------------------------------------------------------------------------------

'this performs asynchronous packet read operation
sub ASyncPacketRead

'wait for CS to go low
do while CS = 1
loop

'indicate that the address bus is not ready for writing
Low AddrReady


'take control of attention acknowledge line and set it low
Low AttnAck


'read packet size header byte
serin Mosi, N57600, packet(0)

'read the rest of the packet
for i = 1 to packet(0)
	if i < packet(0) then
		serin Mosi, N57600, packet(i)
	endif
next

'wait for CS to go high again
do while CS = 0
loop

'set AttnAck high.  Note that this doesn't sit on the SPI bus, so it is free to 
' drive this explicitly.
high AttnAck

endsub