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Faculty of Graduate Studies (Electronic Theses and Practica)
FGS - Electronic Theses and Practica
A built-in testable architecture and design method for on-chip error correction circuits of embedded memories in VLSI/ASIC systems
A built-in testable architecture and design method for on-chip error correction circuits of embedded memories in VLSI/ASIC systems
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Cui_A_built-in.pdf
(5.98 MB)
Date
1994
Authors
Cui, Lianfa
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http://hdl.handle.net/1993/17890
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FGS - Electronic Theses and Practica
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