Xilinx Design Summary

SHARED_MEM_IF Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	79	9,856	1%
Number of 4 input LUTs	193	9,856	1%
Logic Distribution
Number of occupied Slices	141	4,928	2%
Number of Slices containing only related logic	141	141	100%
Number of Slices containing unrelated logic	0	141	0%
Total Number of 4 input LUTs	194	9,856	1%
Number used as logic	193
Number used as a route-thru	1
Number of bonded IOBs	170	396	42%
IOB Flip Flops	138
Number of PPC405s	0	1	0%
Number of GCLKs	1	16	6%
Number of GTs	0	8	0%
Number of GT10s	0	0	0%
Total equivalent gate count for design	3,038
Additional JTAG gate count for IOBs	8,160

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met