Xilinx Design Summary

SNOOPY_IF Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	45	9,856	1%
Number of 4 input LUTs	104	9,856	1%
Logic Distribution
Number of occupied Slices	78	4,928	1%
Number of Slices containing only related logic	78	78	100%
Number of Slices containing unrelated logic	0	78	0%
Total Number of 4 input LUTs	106	9,856	1%
Number used as logic	104
Number used as a route-thru	2
Number of bonded IOBs	141	248	56%
IOB Flip Flops	104
Number of PPC405s	0	1	0%
Number of GCLKs	1	16	6%
Number of GTs	0	8	0%
Number of GT10s	0	0	0%
Total equivalent gate count for design	1,948
Additional JTAG gate count for IOBs	6,768

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met