////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Shared_mem_if_v1_00_a_user_logic_imp_H
#define H_Shared_mem_if_v1_00_a_user_logic_imp_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Shared_mem_if_v1_00_a_user_logic_imp: public HSim__s6 {
public:

    HSim__s4 PE[2];
    HSim__s1 SE[17];

    HSim__s1 SA[11];
  char *t0;
  char t1;
  char t2;
    Shared_mem_if_v1_00_a_user_logic_imp(const char * name);
    ~Shared_mem_if_v1_00_a_user_logic_imp();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createShared_mem_if_v1_00_a_user_logic_imp(const char *name);

#endif
