-------------------------------------------------------------------------------
-- Multiprocs.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity Multiprocs is
  port (
    fpga_0_RS232_Uart_1_RX_pin : in std_logic;
    fpga_0_RS232_Uart_1_TX_pin : out std_logic;
    fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
    fpga_0_DIPSWs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
    fpga_0_PushButtons_5Bit_GPIO_IO_pin : inout std_logic_vector(0 to 4);
    fpga_0_net_gnd_pin : out std_logic;
    fpga_0_net_gnd_1_pin : out std_logic;
    fpga_0_net_gnd_2_pin : out std_logic;
    fpga_0_net_gnd_3_pin : out std_logic;
    fpga_0_net_gnd_4_pin : out std_logic;
    fpga_0_net_gnd_5_pin : out std_logic;
    fpga_0_net_gnd_6_pin : out std_logic;
    sys_clk_pin : in std_logic;
    sys_rst_pin : in std_logic;
    Proc0_External_Mem_Addr_pin : out std_logic_vector(12 downto 0);
    Proc0_External_Mem_Data_Out_pin : out std_logic_vector(15 downto 0);
    Proc0_External_Mem_Data_In_pin : in std_logic_vector(15 downto 0);
    Proc0_External_Mem_RD_WR_pin : out std_logic;
    Proc0_External_Mem_Request_pin : out std_logic;
    Proc0_External_Mem_Ack_out_pin : out std_logic;
    Proc0_External_Mem_Ack_in_pin : in std_logic;
    Proc0_start_task_control_pin : out std_logic;
    Proc0_executing_pin : out std_logic;
    Proc0_iteration_num_pin : in std_logic_vector(15 downto 0);
    Proc0_start_exec_pin : in std_logic;
    Proc0_proc_done_pin : in std_logic;
    Proc0_all_procs_done_pin : in std_logic;
    Proc0_dfg_node_pin : in std_logic_vector(7 downto 0);
    Proc1_External_Mem_Addr_pin : out std_logic_vector(12 downto 0);
    Proc1_External_Mem_Data_Out_pin : out std_logic_vector(15 downto 0);
    Proc1_External_Mem_Data_In_pin : in std_logic_vector(15 downto 0);
    Proc1_External_Mem_RD_WR_pin : out std_logic;
    Proc1_External_Mem_Request_pin : out std_logic;
    Proc1_External_Mem_Ack_out_pin : out std_logic;
    Proc1_External_Mem_Ack_in_pin : in std_logic;
    Proc1_executing_pin : out std_logic;
    Proc1_iteration_num_pin : in std_logic_vector(15 downto 0);
    Proc1_start_exec_pin : in std_logic;
    Proc1_dfg_node_pin : in std_logic_vector(7 downto 0);
    Proc1_proc_done_pin : in std_logic;
    Proc1_all_procs_done_pin : in std_logic;
    snoopy_proc_task_addr_pin : out std_logic_vector(3 downto 0);
    snoopy_info_addr_pin : out std_logic_vector(3 downto 0);
    snoopy_data_pin : in std_logic_vector(31 downto 0);
    Proc2_External_Mem_Addr_pin : out std_logic_vector(12 downto 0);
    Proc2_External_Mem_Data_Out_pin : out std_logic_vector(15 downto 0);
    Proc2_External_Mem_Data_In_pin : in std_logic_vector(15 downto 0);
    Proc2_External_Mem_RD_WR_pin : out std_logic;
    Proc2_External_Mem_Request_pin : out std_logic;
    Proc2_External_Mem_Ack_out_pin : out std_logic;
    Proc2_External_Mem_Ack_in_pin : in std_logic;
    Proc2_executing_pin : out std_logic;
    Proc2_iteration_num_pin : in std_logic_vector(15 downto 0);
    Proc2_start_exec_pin : in std_logic;
    Proc2_dfg_node_pin : in std_logic_vector(7 downto 0);
    Proc2_proc_done_pin : in std_logic;
    Proc2_all_procs_done_pin : in std_logic;
    Proc3_External_Mem_Addr_pin : out std_logic_vector(12 downto 0);
    Proc3_External_Mem_Data_Out_pin : out std_logic_vector(15 downto 0);
    Proc3_External_Mem_Data_In_pin : in std_logic_vector(15 downto 0);
    Proc3_External_Mem_RD_WR_pin : out std_logic;
    Proc3_External_Mem_Request_pin : out std_logic;
    Proc3_External_Mem_Ack_out_pin : out std_logic;
    Proc3_External_Mem_Ack_in_pin : in std_logic;
    Proc3_executing_pin : out std_logic;
    Proc3_iteration_num_pin : in std_logic_vector(15 downto 0);
    Proc3_start_exec_pin : in std_logic;
    Proc3_dfg_node_pin : in std_logic_vector(7 downto 0);
    Proc3_proc_done_pin : in std_logic;
    Proc3_all_procs_done_pin : in std_logic
  );
end Multiprocs;

architecture STRUCTURE of Multiprocs is

  component task_controller_if_3_wrapper is
    port (
      start_task_control : out std_logic;
      executing : out std_logic;
      iteration_num : in std_logic_vector(15 downto 0);
      start_exec : in std_logic;
      dfg_node : in std_logic_vector(7 downto 0);
      proc_done : in std_logic;
      all_procs_done : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component task_controller_if_2_wrapper is
    port (
      start_task_control : out std_logic;
      executing : out std_logic;
      iteration_num : in std_logic_vector(15 downto 0);
      start_exec : in std_logic;
      dfg_node : in std_logic_vector(7 downto 0);
      proc_done : in std_logic;
      all_procs_done : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component task_controller_if_1_wrapper is
    port (
      start_task_control : out std_logic;
      executing : out std_logic;
      iteration_num : in std_logic_vector(15 downto 0);
      start_exec : in std_logic;
      dfg_node : in std_logic_vector(7 downto 0);
      proc_done : in std_logic;
      all_procs_done : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component task_controller_if_0_wrapper is
    port (
      start_task_control : out std_logic;
      executing : out std_logic;
      iteration_num : in std_logic_vector(15 downto 0);
      start_exec : in std_logic;
      dfg_node : in std_logic_vector(7 downto 0);
      proc_done : in std_logic;
      all_procs_done : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component snoopy_if_0_wrapper is
    port (
      proc_task_addr : out std_logic_vector(3 downto 0);
      info_addr : out std_logic_vector(3 downto 0);
      data : in std_logic_vector(31 downto 0);
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component shared_mem_if_3_wrapper is
    port (
      External_Mem_Addr : out std_logic_vector(12 downto 0);
      External_Mem_Data_Out : out std_logic_vector(15 downto 0);
      External_Mem_Data_In : in std_logic_vector(15 downto 0);
      External_Mem_RD_WR : out std_logic;
      External_Mem_Request : out std_logic;
      External_Mem_Ack_out : out std_logic;
      External_Mem_Ack_in : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component shared_mem_if_2_wrapper is
    port (
      External_Mem_Addr : out std_logic_vector(12 downto 0);
      External_Mem_Data_Out : out std_logic_vector(15 downto 0);
      External_Mem_Data_In : in std_logic_vector(15 downto 0);
      External_Mem_RD_WR : out std_logic;
      External_Mem_Request : out std_logic;
      External_Mem_Ack_out : out std_logic;
      External_Mem_Ack_in : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component shared_mem_if_1_wrapper is
    port (
      External_Mem_Addr : out std_logic_vector(12 downto 0);
      External_Mem_Data_Out : out std_logic_vector(15 downto 0);
      External_Mem_Data_In : in std_logic_vector(15 downto 0);
      External_Mem_RD_WR : out std_logic;
      External_Mem_Request : out std_logic;
      External_Mem_Ack_out : out std_logic;
      External_Mem_Ack_in : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component shared_mem_if_0_wrapper is
    port (
      External_Mem_Addr : out std_logic_vector(12 downto 0);
      External_Mem_Data_Out : out std_logic_vector(15 downto 0);
      External_Mem_Data_In : in std_logic_vector(15 downto 0);
      External_Mem_RD_WR : out std_logic;
      External_Mem_Request : out std_logic;
      External_Mem_Ack_out : out std_logic;
      External_Mem_Ack_in : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

  component microblaze_3_wrapper is
    port (
      CLK : in std_logic;
      RESET : in std_logic;
      INTERRUPT : in std_logic;
      DEBUG_RST : in std_logic;
      EXT_BRK : in std_logic;
      EXT_NM_BRK : in std_logic;
      DBG_STOP : in std_logic;
      MB_Halted : out std_logic;
      INSTR : in std_logic_vector(0 to 31);
      I_ADDRTAG : out std_logic_vector(0 to 3);
      IREADY : in std_logic;
      IWAIT : in std_logic;
      INSTR_ADDR : out std_logic_vector(0 to 31);
      IFETCH : out std_logic;
      I_AS : out std_logic;
      DATA_READ : in std_logic_vector(0 to 31);
      DREADY : in std_logic;
      DWAIT : in std_logic;
      DATA_WRITE : out std_logic_vector(0 to 31);
      DATA_ADDR : out std_logic_vector(0 to 31);
      D_ADDRTAG : out std_logic_vector(0 to 3);
      D_AS : out std_logic;
      READ_STROBE : out std_logic;
      WRITE_STROBE : out std_logic;
      BYTE_ENABLE : out std_logic_vector(0 to 3);
      DM_ABUS : out std_logic_vector(0 to 31);
      DM_BE : out std_logic_vector(0 to 3);
      DM_BUSLOCK : out std_logic;
      DM_DBUS : out std_logic_vector(0 to 31);
      DM_REQUEST : out std_logic;
      DM_RNW : out std_logic;
      DM_SELECT : out std_logic;
      DM_SEQADDR : out std_logic;
      DOPB_DBUS : in std_logic_vector(0 to 31);
      DOPB_ERRACK : in std_logic;
      DOPB_MGRANT : in std_logic;
      DOPB_RETRY : in std_logic;
      DOPB_TIMEOUT : in std_logic;
      DOPB_XFERACK : in std_logic;
      IM_ABUS : out std_logic_vector(0 to 31);
      IM_BE : out std_logic_vector(0 to 3);
      IM_BUSLOCK : out std_logic;
      IM_DBUS : out std_logic_vector(0 to 31);
      IM_REQUEST : out std_logic;
      IM_RNW : out std_logic;
      IM_SELECT : out std_logic;
      IM_SEQADDR : out std_logic;
      IOPB_DBUS : in std_logic_vector(0 to 31);
      IOPB_ERRACK : in std_logic;
      IOPB_MGRANT : in std_logic;
      IOPB_RETRY : in std_logic;
      IOPB_TIMEOUT : in std_logic;
      IOPB_XFERACK : in std_logic;
      DBG_CLK : in std_logic;
      DBG_TDI : in std_logic;
      DBG_TDO : out std_logic;
      DBG_REG_EN : in std_logic_vector(0 to 4);
      DBG_CAPTURE : in std_logic;
      DBG_UPDATE : in std_logic;
      Trace_Instruction : out std_logic_vector(0 to 31);
      Trace_Valid_Instr : out std_logic;
      Trace_PC : out std_logic_vector(0 to 31);
      Trace_Reg_Write : out std_logic;
      Trace_Reg_Addr : out std_logic_vector(0 to 4);
      Trace_MSR_Reg : out std_logic_vector(0 to 10);
      Trace_New_Reg_Value : out std_logic_vector(0 to 31);
      Trace_Exception_Taken : out std_logic;
      Trace_Exception_Kind : out std_logic_vector(0 to 3);
      Trace_Jump_Taken : out std_logic;
      Trace_Delay_Slot : out std_logic;
      Trace_Data_Address : out std_logic_vector(0 to 31);
      Trace_Data_Access : out std_logic;
      Trace_Data_Read : out std_logic;
      Trace_Data_Write : out std_logic;
      Trace_Data_Write_Value : out std_logic_vector(0 to 31);
      Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
      Trace_DCache_Req : out std_logic;
      Trace_DCache_Hit : out std_logic;
      Trace_ICache_Req : out std_logic;
      Trace_ICache_Hit : out std_logic;
      Trace_OF_PipeRun : out std_logic;
      Trace_EX_PipeRun : out std_logic;
      Trace_MEM_PipeRun : out std_logic;
      FSL0_S_CLK : out std_logic;
      FSL0_S_READ : out std_logic;
      FSL0_S_DATA : in std_logic_vector(0 to 31);
      FSL0_S_CONTROL : in std_logic;
      FSL0_S_EXISTS : in std_logic;
      FSL0_M_CLK : out std_logic;
      FSL0_M_WRITE : out std_logic;
      FSL0_M_DATA : out std_logic_vector(0 to 31);
      FSL0_M_CONTROL : out std_logic;
      FSL0_M_FULL : in std_logic;
      FSL1_S_CLK : out std_logic;
      FSL1_S_READ : out std_logic;
      FSL1_S_DATA : in std_logic_vector(0 to 31);
      FSL1_S_CONTROL : in std_logic;
      FSL1_S_EXISTS : in std_logic;
      FSL1_M_CLK : out std_logic;
      FSL1_M_WRITE : out std_logic;
      FSL1_M_DATA : out std_logic_vector(0 to 31);
      FSL1_M_CONTROL : out std_logic;
      FSL1_M_FULL : in std_logic;
      FSL2_S_CLK : out std_logic;
      FSL2_S_READ : out std_logic;
      FSL2_S_DATA : in std_logic_vector(0 to 31);
      FSL2_S_CONTROL : in std_logic;
      FSL2_S_EXISTS : in std_logic;
      FSL2_M_CLK : out std_logic;
      FSL2_M_WRITE : out std_logic;
      FSL2_M_DATA : out std_logic_vector(0 to 31);
      FSL2_M_CONTROL : out std_logic;
      FSL2_M_FULL : in std_logic;
      FSL3_S_CLK : out std_logic;
      FSL3_S_READ : out std_logic;
      FSL3_S_DATA : in std_logic_vector(0 to 31);
      FSL3_S_CONTROL : in std_logic;
      FSL3_S_EXISTS : in std_logic;
      FSL3_M_CLK : out std_logic;
      FSL3_M_WRITE : out std_logic;
      FSL3_M_DATA : out std_logic_vector(0 to 31);
      FSL3_M_CONTROL : out std_logic;
      FSL3_M_FULL : in std_logic;
      FSL4_S_CLK : out std_logic;
      FSL4_S_READ : out std_logic;
      FSL4_S_DATA : in std_logic_vector(0 to 31);
      FSL4_S_CONTROL : in std_logic;
      FSL4_S_EXISTS : in std_logic;
      FSL4_M_CLK : out std_logic;
      FSL4_M_WRITE : out std_logic;
      FSL4_M_DATA : out std_logic_vector(0 to 31);
      FSL4_M_CONTROL : out std_logic;
      FSL4_M_FULL : in std_logic;
      FSL5_S_CLK : out std_logic;
      FSL5_S_READ : out std_logic;
      FSL5_S_DATA : in std_logic_vector(0 to 31);
      FSL5_S_CONTROL : in std_logic;
      FSL5_S_EXISTS : in std_logic;
      FSL5_M_CLK : out std_logic;
      FSL5_M_WRITE : out std_logic;
      FSL5_M_DATA : out std_logic_vector(0 to 31);
      FSL5_M_CONTROL : out std_logic;
      FSL5_M_FULL : in std_logic;
      FSL6_S_CLK : out std_logic;
      FSL6_S_READ : out std_logic;
      FSL6_S_DATA : in std_logic_vector(0 to 31);
      FSL6_S_CONTROL : in std_logic;
      FSL6_S_EXISTS : in std_logic;
      FSL6_M_CLK : out std_logic;
      FSL6_M_WRITE : out std_logic;
      FSL6_M_DATA : out std_logic_vector(0 to 31);
      FSL6_M_CONTROL : out std_logic;
      FSL6_M_FULL : in std_logic;
      FSL7_S_CLK : out std_logic;
      FSL7_S_READ : out std_logic;
      FSL7_S_DATA : in std_logic_vector(0 to 31);
      FSL7_S_CONTROL : in std_logic;
      FSL7_S_EXISTS : in std_logic;
      FSL7_M_CLK : out std_logic;
      FSL7_M_WRITE : out std_logic;
      FSL7_M_DATA : out std_logic_vector(0 to 31);
      FSL7_M_CONTROL : out std_logic;
      FSL7_M_FULL : in std_logic;
      ICACHE_FSL_IN_CLK : out std_logic;
      ICACHE_FSL_IN_READ : out std_logic;
      ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      ICACHE_FSL_IN_CONTROL : in std_logic;
      ICACHE_FSL_IN_EXISTS : in std_logic;
      ICACHE_FSL_OUT_CLK : out std_logic;
      ICACHE_FSL_OUT_WRITE : out std_logic;
      ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      ICACHE_FSL_OUT_CONTROL : out std_logic;
      ICACHE_FSL_OUT_FULL : in std_logic;
      DCACHE_FSL_IN_CLK : out std_logic;
      DCACHE_FSL_IN_READ : out std_logic;
      DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      DCACHE_FSL_IN_CONTROL : in std_logic;
      DCACHE_FSL_IN_EXISTS : in std_logic;
      DCACHE_FSL_OUT_CLK : out std_logic;
      DCACHE_FSL_OUT_WRITE : out std_logic;
      DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      DCACHE_FSL_OUT_CONTROL : out std_logic;
      DCACHE_FSL_OUT_FULL : in std_logic
    );
  end component;

  component microblaze_2_wrapper is
    port (
      CLK : in std_logic;
      RESET : in std_logic;
      INTERRUPT : in std_logic;
      DEBUG_RST : in std_logic;
      EXT_BRK : in std_logic;
      EXT_NM_BRK : in std_logic;
      DBG_STOP : in std_logic;
      MB_Halted : out std_logic;
      INSTR : in std_logic_vector(0 to 31);
      I_ADDRTAG : out std_logic_vector(0 to 3);
      IREADY : in std_logic;
      IWAIT : in std_logic;
      INSTR_ADDR : out std_logic_vector(0 to 31);
      IFETCH : out std_logic;
      I_AS : out std_logic;
      DATA_READ : in std_logic_vector(0 to 31);
      DREADY : in std_logic;
      DWAIT : in std_logic;
      DATA_WRITE : out std_logic_vector(0 to 31);
      DATA_ADDR : out std_logic_vector(0 to 31);
      D_ADDRTAG : out std_logic_vector(0 to 3);
      D_AS : out std_logic;
      READ_STROBE : out std_logic;
      WRITE_STROBE : out std_logic;
      BYTE_ENABLE : out std_logic_vector(0 to 3);
      DM_ABUS : out std_logic_vector(0 to 31);
      DM_BE : out std_logic_vector(0 to 3);
      DM_BUSLOCK : out std_logic;
      DM_DBUS : out std_logic_vector(0 to 31);
      DM_REQUEST : out std_logic;
      DM_RNW : out std_logic;
      DM_SELECT : out std_logic;
      DM_SEQADDR : out std_logic;
      DOPB_DBUS : in std_logic_vector(0 to 31);
      DOPB_ERRACK : in std_logic;
      DOPB_MGRANT : in std_logic;
      DOPB_RETRY : in std_logic;
      DOPB_TIMEOUT : in std_logic;
      DOPB_XFERACK : in std_logic;
      IM_ABUS : out std_logic_vector(0 to 31);
      IM_BE : out std_logic_vector(0 to 3);
      IM_BUSLOCK : out std_logic;
      IM_DBUS : out std_logic_vector(0 to 31);
      IM_REQUEST : out std_logic;
      IM_RNW : out std_logic;
      IM_SELECT : out std_logic;
      IM_SEQADDR : out std_logic;
      IOPB_DBUS : in std_logic_vector(0 to 31);
      IOPB_ERRACK : in std_logic;
      IOPB_MGRANT : in std_logic;
      IOPB_RETRY : in std_logic;
      IOPB_TIMEOUT : in std_logic;
      IOPB_XFERACK : in std_logic;
      DBG_CLK : in std_logic;
      DBG_TDI : in std_logic;
      DBG_TDO : out std_logic;
      DBG_REG_EN : in std_logic_vector(0 to 4);
      DBG_CAPTURE : in std_logic;
      DBG_UPDATE : in std_logic;
      Trace_Instruction : out std_logic_vector(0 to 31);
      Trace_Valid_Instr : out std_logic;
      Trace_PC : out std_logic_vector(0 to 31);
      Trace_Reg_Write : out std_logic;
      Trace_Reg_Addr : out std_logic_vector(0 to 4);
      Trace_MSR_Reg : out std_logic_vector(0 to 10);
      Trace_New_Reg_Value : out std_logic_vector(0 to 31);
      Trace_Exception_Taken : out std_logic;
      Trace_Exception_Kind : out std_logic_vector(0 to 3);
      Trace_Jump_Taken : out std_logic;
      Trace_Delay_Slot : out std_logic;
      Trace_Data_Address : out std_logic_vector(0 to 31);
      Trace_Data_Access : out std_logic;
      Trace_Data_Read : out std_logic;
      Trace_Data_Write : out std_logic;
      Trace_Data_Write_Value : out std_logic_vector(0 to 31);
      Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
      Trace_DCache_Req : out std_logic;
      Trace_DCache_Hit : out std_logic;
      Trace_ICache_Req : out std_logic;
      Trace_ICache_Hit : out std_logic;
      Trace_OF_PipeRun : out std_logic;
      Trace_EX_PipeRun : out std_logic;
      Trace_MEM_PipeRun : out std_logic;
      FSL0_S_CLK : out std_logic;
      FSL0_S_READ : out std_logic;
      FSL0_S_DATA : in std_logic_vector(0 to 31);
      FSL0_S_CONTROL : in std_logic;
      FSL0_S_EXISTS : in std_logic;
      FSL0_M_CLK : out std_logic;
      FSL0_M_WRITE : out std_logic;
      FSL0_M_DATA : out std_logic_vector(0 to 31);
      FSL0_M_CONTROL : out std_logic;
      FSL0_M_FULL : in std_logic;
      FSL1_S_CLK : out std_logic;
      FSL1_S_READ : out std_logic;
      FSL1_S_DATA : in std_logic_vector(0 to 31);
      FSL1_S_CONTROL : in std_logic;
      FSL1_S_EXISTS : in std_logic;
      FSL1_M_CLK : out std_logic;
      FSL1_M_WRITE : out std_logic;
      FSL1_M_DATA : out std_logic_vector(0 to 31);
      FSL1_M_CONTROL : out std_logic;
      FSL1_M_FULL : in std_logic;
      FSL2_S_CLK : out std_logic;
      FSL2_S_READ : out std_logic;
      FSL2_S_DATA : in std_logic_vector(0 to 31);
      FSL2_S_CONTROL : in std_logic;
      FSL2_S_EXISTS : in std_logic;
      FSL2_M_CLK : out std_logic;
      FSL2_M_WRITE : out std_logic;
      FSL2_M_DATA : out std_logic_vector(0 to 31);
      FSL2_M_CONTROL : out std_logic;
      FSL2_M_FULL : in std_logic;
      FSL3_S_CLK : out std_logic;
      FSL3_S_READ : out std_logic;
      FSL3_S_DATA : in std_logic_vector(0 to 31);
      FSL3_S_CONTROL : in std_logic;
      FSL3_S_EXISTS : in std_logic;
      FSL3_M_CLK : out std_logic;
      FSL3_M_WRITE : out std_logic;
      FSL3_M_DATA : out std_logic_vector(0 to 31);
      FSL3_M_CONTROL : out std_logic;
      FSL3_M_FULL : in std_logic;
      FSL4_S_CLK : out std_logic;
      FSL4_S_READ : out std_logic;
      FSL4_S_DATA : in std_logic_vector(0 to 31);
      FSL4_S_CONTROL : in std_logic;
      FSL4_S_EXISTS : in std_logic;
      FSL4_M_CLK : out std_logic;
      FSL4_M_WRITE : out std_logic;
      FSL4_M_DATA : out std_logic_vector(0 to 31);
      FSL4_M_CONTROL : out std_logic;
      FSL4_M_FULL : in std_logic;
      FSL5_S_CLK : out std_logic;
      FSL5_S_READ : out std_logic;
      FSL5_S_DATA : in std_logic_vector(0 to 31);
      FSL5_S_CONTROL : in std_logic;
      FSL5_S_EXISTS : in std_logic;
      FSL5_M_CLK : out std_logic;
      FSL5_M_WRITE : out std_logic;
      FSL5_M_DATA : out std_logic_vector(0 to 31);
      FSL5_M_CONTROL : out std_logic;
      FSL5_M_FULL : in std_logic;
      FSL6_S_CLK : out std_logic;
      FSL6_S_READ : out std_logic;
      FSL6_S_DATA : in std_logic_vector(0 to 31);
      FSL6_S_CONTROL : in std_logic;
      FSL6_S_EXISTS : in std_logic;
      FSL6_M_CLK : out std_logic;
      FSL6_M_WRITE : out std_logic;
      FSL6_M_DATA : out std_logic_vector(0 to 31);
      FSL6_M_CONTROL : out std_logic;
      FSL6_M_FULL : in std_logic;
      FSL7_S_CLK : out std_logic;
      FSL7_S_READ : out std_logic;
      FSL7_S_DATA : in std_logic_vector(0 to 31);
      FSL7_S_CONTROL : in std_logic;
      FSL7_S_EXISTS : in std_logic;
      FSL7_M_CLK : out std_logic;
      FSL7_M_WRITE : out std_logic;
      FSL7_M_DATA : out std_logic_vector(0 to 31);
      FSL7_M_CONTROL : out std_logic;
      FSL7_M_FULL : in std_logic;
      ICACHE_FSL_IN_CLK : out std_logic;
      ICACHE_FSL_IN_READ : out std_logic;
      ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      ICACHE_FSL_IN_CONTROL : in std_logic;
      ICACHE_FSL_IN_EXISTS : in std_logic;
      ICACHE_FSL_OUT_CLK : out std_logic;
      ICACHE_FSL_OUT_WRITE : out std_logic;
      ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      ICACHE_FSL_OUT_CONTROL : out std_logic;
      ICACHE_FSL_OUT_FULL : in std_logic;
      DCACHE_FSL_IN_CLK : out std_logic;
      DCACHE_FSL_IN_READ : out std_logic;
      DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      DCACHE_FSL_IN_CONTROL : in std_logic;
      DCACHE_FSL_IN_EXISTS : in std_logic;
      DCACHE_FSL_OUT_CLK : out std_logic;
      DCACHE_FSL_OUT_WRITE : out std_logic;
      DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      DCACHE_FSL_OUT_CONTROL : out std_logic;
      DCACHE_FSL_OUT_FULL : in std_logic
    );
  end component;

  component microblaze_1_wrapper is
    port (
      CLK : in std_logic;
      RESET : in std_logic;
      INTERRUPT : in std_logic;
      DEBUG_RST : in std_logic;
      EXT_BRK : in std_logic;
      EXT_NM_BRK : in std_logic;
      DBG_STOP : in std_logic;
      MB_Halted : out std_logic;
      INSTR : in std_logic_vector(0 to 31);
      I_ADDRTAG : out std_logic_vector(0 to 3);
      IREADY : in std_logic;
      IWAIT : in std_logic;
      INSTR_ADDR : out std_logic_vector(0 to 31);
      IFETCH : out std_logic;
      I_AS : out std_logic;
      DATA_READ : in std_logic_vector(0 to 31);
      DREADY : in std_logic;
      DWAIT : in std_logic;
      DATA_WRITE : out std_logic_vector(0 to 31);
      DATA_ADDR : out std_logic_vector(0 to 31);
      D_ADDRTAG : out std_logic_vector(0 to 3);
      D_AS : out std_logic;
      READ_STROBE : out std_logic;
      WRITE_STROBE : out std_logic;
      BYTE_ENABLE : out std_logic_vector(0 to 3);
      DM_ABUS : out std_logic_vector(0 to 31);
      DM_BE : out std_logic_vector(0 to 3);
      DM_BUSLOCK : out std_logic;
      DM_DBUS : out std_logic_vector(0 to 31);
      DM_REQUEST : out std_logic;
      DM_RNW : out std_logic;
      DM_SELECT : out std_logic;
      DM_SEQADDR : out std_logic;
      DOPB_DBUS : in std_logic_vector(0 to 31);
      DOPB_ERRACK : in std_logic;
      DOPB_MGRANT : in std_logic;
      DOPB_RETRY : in std_logic;
      DOPB_TIMEOUT : in std_logic;
      DOPB_XFERACK : in std_logic;
      IM_ABUS : out std_logic_vector(0 to 31);
      IM_BE : out std_logic_vector(0 to 3);
      IM_BUSLOCK : out std_logic;
      IM_DBUS : out std_logic_vector(0 to 31);
      IM_REQUEST : out std_logic;
      IM_RNW : out std_logic;
      IM_SELECT : out std_logic;
      IM_SEQADDR : out std_logic;
      IOPB_DBUS : in std_logic_vector(0 to 31);
      IOPB_ERRACK : in std_logic;
      IOPB_MGRANT : in std_logic;
      IOPB_RETRY : in std_logic;
      IOPB_TIMEOUT : in std_logic;
      IOPB_XFERACK : in std_logic;
      DBG_CLK : in std_logic;
      DBG_TDI : in std_logic;
      DBG_TDO : out std_logic;
      DBG_REG_EN : in std_logic_vector(0 to 4);
      DBG_CAPTURE : in std_logic;
      DBG_UPDATE : in std_logic;
      Trace_Instruction : out std_logic_vector(0 to 31);
      Trace_Valid_Instr : out std_logic;
      Trace_PC : out std_logic_vector(0 to 31);
      Trace_Reg_Write : out std_logic;
      Trace_Reg_Addr : out std_logic_vector(0 to 4);
      Trace_MSR_Reg : out std_logic_vector(0 to 10);
      Trace_New_Reg_Value : out std_logic_vector(0 to 31);
      Trace_Exception_Taken : out std_logic;
      Trace_Exception_Kind : out std_logic_vector(0 to 3);
      Trace_Jump_Taken : out std_logic;
      Trace_Delay_Slot : out std_logic;
      Trace_Data_Address : out std_logic_vector(0 to 31);
      Trace_Data_Access : out std_logic;
      Trace_Data_Read : out std_logic;
      Trace_Data_Write : out std_logic;
      Trace_Data_Write_Value : out std_logic_vector(0 to 31);
      Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
      Trace_DCache_Req : out std_logic;
      Trace_DCache_Hit : out std_logic;
      Trace_ICache_Req : out std_logic;
      Trace_ICache_Hit : out std_logic;
      Trace_OF_PipeRun : out std_logic;
      Trace_EX_PipeRun : out std_logic;
      Trace_MEM_PipeRun : out std_logic;
      FSL0_S_CLK : out std_logic;
      FSL0_S_READ : out std_logic;
      FSL0_S_DATA : in std_logic_vector(0 to 31);
      FSL0_S_CONTROL : in std_logic;
      FSL0_S_EXISTS : in std_logic;
      FSL0_M_CLK : out std_logic;
      FSL0_M_WRITE : out std_logic;
      FSL0_M_DATA : out std_logic_vector(0 to 31);
      FSL0_M_CONTROL : out std_logic;
      FSL0_M_FULL : in std_logic;
      FSL1_S_CLK : out std_logic;
      FSL1_S_READ : out std_logic;
      FSL1_S_DATA : in std_logic_vector(0 to 31);
      FSL1_S_CONTROL : in std_logic;
      FSL1_S_EXISTS : in std_logic;
      FSL1_M_CLK : out std_logic;
      FSL1_M_WRITE : out std_logic;
      FSL1_M_DATA : out std_logic_vector(0 to 31);
      FSL1_M_CONTROL : out std_logic;
      FSL1_M_FULL : in std_logic;
      FSL2_S_CLK : out std_logic;
      FSL2_S_READ : out std_logic;
      FSL2_S_DATA : in std_logic_vector(0 to 31);
      FSL2_S_CONTROL : in std_logic;
      FSL2_S_EXISTS : in std_logic;
      FSL2_M_CLK : out std_logic;
      FSL2_M_WRITE : out std_logic;
      FSL2_M_DATA : out std_logic_vector(0 to 31);
      FSL2_M_CONTROL : out std_logic;
      FSL2_M_FULL : in std_logic;
      FSL3_S_CLK : out std_logic;
      FSL3_S_READ : out std_logic;
      FSL3_S_DATA : in std_logic_vector(0 to 31);
      FSL3_S_CONTROL : in std_logic;
      FSL3_S_EXISTS : in std_logic;
      FSL3_M_CLK : out std_logic;
      FSL3_M_WRITE : out std_logic;
      FSL3_M_DATA : out std_logic_vector(0 to 31);
      FSL3_M_CONTROL : out std_logic;
      FSL3_M_FULL : in std_logic;
      FSL4_S_CLK : out std_logic;
      FSL4_S_READ : out std_logic;
      FSL4_S_DATA : in std_logic_vector(0 to 31);
      FSL4_S_CONTROL : in std_logic;
      FSL4_S_EXISTS : in std_logic;
      FSL4_M_CLK : out std_logic;
      FSL4_M_WRITE : out std_logic;
      FSL4_M_DATA : out std_logic_vector(0 to 31);
      FSL4_M_CONTROL : out std_logic;
      FSL4_M_FULL : in std_logic;
      FSL5_S_CLK : out std_logic;
      FSL5_S_READ : out std_logic;
      FSL5_S_DATA : in std_logic_vector(0 to 31);
      FSL5_S_CONTROL : in std_logic;
      FSL5_S_EXISTS : in std_logic;
      FSL5_M_CLK : out std_logic;
      FSL5_M_WRITE : out std_logic;
      FSL5_M_DATA : out std_logic_vector(0 to 31);
      FSL5_M_CONTROL : out std_logic;
      FSL5_M_FULL : in std_logic;
      FSL6_S_CLK : out std_logic;
      FSL6_S_READ : out std_logic;
      FSL6_S_DATA : in std_logic_vector(0 to 31);
      FSL6_S_CONTROL : in std_logic;
      FSL6_S_EXISTS : in std_logic;
      FSL6_M_CLK : out std_logic;
      FSL6_M_WRITE : out std_logic;
      FSL6_M_DATA : out std_logic_vector(0 to 31);
      FSL6_M_CONTROL : out std_logic;
      FSL6_M_FULL : in std_logic;
      FSL7_S_CLK : out std_logic;
      FSL7_S_READ : out std_logic;
      FSL7_S_DATA : in std_logic_vector(0 to 31);
      FSL7_S_CONTROL : in std_logic;
      FSL7_S_EXISTS : in std_logic;
      FSL7_M_CLK : out std_logic;
      FSL7_M_WRITE : out std_logic;
      FSL7_M_DATA : out std_logic_vector(0 to 31);
      FSL7_M_CONTROL : out std_logic;
      FSL7_M_FULL : in std_logic;
      ICACHE_FSL_IN_CLK : out std_logic;
      ICACHE_FSL_IN_READ : out std_logic;
      ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      ICACHE_FSL_IN_CONTROL : in std_logic;
      ICACHE_FSL_IN_EXISTS : in std_logic;
      ICACHE_FSL_OUT_CLK : out std_logic;
      ICACHE_FSL_OUT_WRITE : out std_logic;
      ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      ICACHE_FSL_OUT_CONTROL : out std_logic;
      ICACHE_FSL_OUT_FULL : in std_logic;
      DCACHE_FSL_IN_CLK : out std_logic;
      DCACHE_FSL_IN_READ : out std_logic;
      DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      DCACHE_FSL_IN_CONTROL : in std_logic;
      DCACHE_FSL_IN_EXISTS : in std_logic;
      DCACHE_FSL_OUT_CLK : out std_logic;
      DCACHE_FSL_OUT_WRITE : out std_logic;
      DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      DCACHE_FSL_OUT_CONTROL : out std_logic;
      DCACHE_FSL_OUT_FULL : in std_logic
    );
  end component;

  component microblaze_0_wrapper is
    port (
      CLK : in std_logic;
      RESET : in std_logic;
      INTERRUPT : in std_logic;
      DEBUG_RST : in std_logic;
      EXT_BRK : in std_logic;
      EXT_NM_BRK : in std_logic;
      DBG_STOP : in std_logic;
      MB_Halted : out std_logic;
      INSTR : in std_logic_vector(0 to 31);
      I_ADDRTAG : out std_logic_vector(0 to 3);
      IREADY : in std_logic;
      IWAIT : in std_logic;
      INSTR_ADDR : out std_logic_vector(0 to 31);
      IFETCH : out std_logic;
      I_AS : out std_logic;
      DATA_READ : in std_logic_vector(0 to 31);
      DREADY : in std_logic;
      DWAIT : in std_logic;
      DATA_WRITE : out std_logic_vector(0 to 31);
      DATA_ADDR : out std_logic_vector(0 to 31);
      D_ADDRTAG : out std_logic_vector(0 to 3);
      D_AS : out std_logic;
      READ_STROBE : out std_logic;
      WRITE_STROBE : out std_logic;
      BYTE_ENABLE : out std_logic_vector(0 to 3);
      DM_ABUS : out std_logic_vector(0 to 31);
      DM_BE : out std_logic_vector(0 to 3);
      DM_BUSLOCK : out std_logic;
      DM_DBUS : out std_logic_vector(0 to 31);
      DM_REQUEST : out std_logic;
      DM_RNW : out std_logic;
      DM_SELECT : out std_logic;
      DM_SEQADDR : out std_logic;
      DOPB_DBUS : in std_logic_vector(0 to 31);
      DOPB_ERRACK : in std_logic;
      DOPB_MGRANT : in std_logic;
      DOPB_RETRY : in std_logic;
      DOPB_TIMEOUT : in std_logic;
      DOPB_XFERACK : in std_logic;
      IM_ABUS : out std_logic_vector(0 to 31);
      IM_BE : out std_logic_vector(0 to 3);
      IM_BUSLOCK : out std_logic;
      IM_DBUS : out std_logic_vector(0 to 31);
      IM_REQUEST : out std_logic;
      IM_RNW : out std_logic;
      IM_SELECT : out std_logic;
      IM_SEQADDR : out std_logic;
      IOPB_DBUS : in std_logic_vector(0 to 31);
      IOPB_ERRACK : in std_logic;
      IOPB_MGRANT : in std_logic;
      IOPB_RETRY : in std_logic;
      IOPB_TIMEOUT : in std_logic;
      IOPB_XFERACK : in std_logic;
      DBG_CLK : in std_logic;
      DBG_TDI : in std_logic;
      DBG_TDO : out std_logic;
      DBG_REG_EN : in std_logic_vector(0 to 4);
      DBG_CAPTURE : in std_logic;
      DBG_UPDATE : in std_logic;
      Trace_Instruction : out std_logic_vector(0 to 31);
      Trace_Valid_Instr : out std_logic;
      Trace_PC : out std_logic_vector(0 to 31);
      Trace_Reg_Write : out std_logic;
      Trace_Reg_Addr : out std_logic_vector(0 to 4);
      Trace_MSR_Reg : out std_logic_vector(0 to 10);
      Trace_New_Reg_Value : out std_logic_vector(0 to 31);
      Trace_Exception_Taken : out std_logic;
      Trace_Exception_Kind : out std_logic_vector(0 to 3);
      Trace_Jump_Taken : out std_logic;
      Trace_Delay_Slot : out std_logic;
      Trace_Data_Address : out std_logic_vector(0 to 31);
      Trace_Data_Access : out std_logic;
      Trace_Data_Read : out std_logic;
      Trace_Data_Write : out std_logic;
      Trace_Data_Write_Value : out std_logic_vector(0 to 31);
      Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
      Trace_DCache_Req : out std_logic;
      Trace_DCache_Hit : out std_logic;
      Trace_ICache_Req : out std_logic;
      Trace_ICache_Hit : out std_logic;
      Trace_OF_PipeRun : out std_logic;
      Trace_EX_PipeRun : out std_logic;
      Trace_MEM_PipeRun : out std_logic;
      FSL0_S_CLK : out std_logic;
      FSL0_S_READ : out std_logic;
      FSL0_S_DATA : in std_logic_vector(0 to 31);
      FSL0_S_CONTROL : in std_logic;
      FSL0_S_EXISTS : in std_logic;
      FSL0_M_CLK : out std_logic;
      FSL0_M_WRITE : out std_logic;
      FSL0_M_DATA : out std_logic_vector(0 to 31);
      FSL0_M_CONTROL : out std_logic;
      FSL0_M_FULL : in std_logic;
      FSL1_S_CLK : out std_logic;
      FSL1_S_READ : out std_logic;
      FSL1_S_DATA : in std_logic_vector(0 to 31);
      FSL1_S_CONTROL : in std_logic;
      FSL1_S_EXISTS : in std_logic;
      FSL1_M_CLK : out std_logic;
      FSL1_M_WRITE : out std_logic;
      FSL1_M_DATA : out std_logic_vector(0 to 31);
      FSL1_M_CONTROL : out std_logic;
      FSL1_M_FULL : in std_logic;
      FSL2_S_CLK : out std_logic;
      FSL2_S_READ : out std_logic;
      FSL2_S_DATA : in std_logic_vector(0 to 31);
      FSL2_S_CONTROL : in std_logic;
      FSL2_S_EXISTS : in std_logic;
      FSL2_M_CLK : out std_logic;
      FSL2_M_WRITE : out std_logic;
      FSL2_M_DATA : out std_logic_vector(0 to 31);
      FSL2_M_CONTROL : out std_logic;
      FSL2_M_FULL : in std_logic;
      FSL3_S_CLK : out std_logic;
      FSL3_S_READ : out std_logic;
      FSL3_S_DATA : in std_logic_vector(0 to 31);
      FSL3_S_CONTROL : in std_logic;
      FSL3_S_EXISTS : in std_logic;
      FSL3_M_CLK : out std_logic;
      FSL3_M_WRITE : out std_logic;
      FSL3_M_DATA : out std_logic_vector(0 to 31);
      FSL3_M_CONTROL : out std_logic;
      FSL3_M_FULL : in std_logic;
      FSL4_S_CLK : out std_logic;
      FSL4_S_READ : out std_logic;
      FSL4_S_DATA : in std_logic_vector(0 to 31);
      FSL4_S_CONTROL : in std_logic;
      FSL4_S_EXISTS : in std_logic;
      FSL4_M_CLK : out std_logic;
      FSL4_M_WRITE : out std_logic;
      FSL4_M_DATA : out std_logic_vector(0 to 31);
      FSL4_M_CONTROL : out std_logic;
      FSL4_M_FULL : in std_logic;
      FSL5_S_CLK : out std_logic;
      FSL5_S_READ : out std_logic;
      FSL5_S_DATA : in std_logic_vector(0 to 31);
      FSL5_S_CONTROL : in std_logic;
      FSL5_S_EXISTS : in std_logic;
      FSL5_M_CLK : out std_logic;
      FSL5_M_WRITE : out std_logic;
      FSL5_M_DATA : out std_logic_vector(0 to 31);
      FSL5_M_CONTROL : out std_logic;
      FSL5_M_FULL : in std_logic;
      FSL6_S_CLK : out std_logic;
      FSL6_S_READ : out std_logic;
      FSL6_S_DATA : in std_logic_vector(0 to 31);
      FSL6_S_CONTROL : in std_logic;
      FSL6_S_EXISTS : in std_logic;
      FSL6_M_CLK : out std_logic;
      FSL6_M_WRITE : out std_logic;
      FSL6_M_DATA : out std_logic_vector(0 to 31);
      FSL6_M_CONTROL : out std_logic;
      FSL6_M_FULL : in std_logic;
      FSL7_S_CLK : out std_logic;
      FSL7_S_READ : out std_logic;
      FSL7_S_DATA : in std_logic_vector(0 to 31);
      FSL7_S_CONTROL : in std_logic;
      FSL7_S_EXISTS : in std_logic;
      FSL7_M_CLK : out std_logic;
      FSL7_M_WRITE : out std_logic;
      FSL7_M_DATA : out std_logic_vector(0 to 31);
      FSL7_M_CONTROL : out std_logic;
      FSL7_M_FULL : in std_logic;
      ICACHE_FSL_IN_CLK : out std_logic;
      ICACHE_FSL_IN_READ : out std_logic;
      ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      ICACHE_FSL_IN_CONTROL : in std_logic;
      ICACHE_FSL_IN_EXISTS : in std_logic;
      ICACHE_FSL_OUT_CLK : out std_logic;
      ICACHE_FSL_OUT_WRITE : out std_logic;
      ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      ICACHE_FSL_OUT_CONTROL : out std_logic;
      ICACHE_FSL_OUT_FULL : in std_logic;
      DCACHE_FSL_IN_CLK : out std_logic;
      DCACHE_FSL_IN_READ : out std_logic;
      DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
      DCACHE_FSL_IN_CONTROL : in std_logic;
      DCACHE_FSL_IN_EXISTS : in std_logic;
      DCACHE_FSL_OUT_CLK : out std_logic;
      DCACHE_FSL_OUT_WRITE : out std_logic;
      DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
      DCACHE_FSL_OUT_CONTROL : out std_logic;
      DCACHE_FSL_OUT_FULL : in std_logic
    );
  end component;

  component lmb_bram_wrapper is
    port (
      BRAM_Rst_A : in std_logic;
      BRAM_Clk_A : in std_logic;
      BRAM_EN_A : in std_logic;
      BRAM_WEN_A : in std_logic_vector(0 to 3);
      BRAM_Addr_A : in std_logic_vector(0 to 31);
      BRAM_Din_A : out std_logic_vector(0 to 31);
      BRAM_Dout_A : in std_logic_vector(0 to 31);
      BRAM_Rst_B : in std_logic;
      BRAM_Clk_B : in std_logic;
      BRAM_EN_B : in std_logic;
      BRAM_WEN_B : in std_logic_vector(0 to 3);
      BRAM_Addr_B : in std_logic_vector(0 to 31);
      BRAM_Din_B : out std_logic_vector(0 to 31);
      BRAM_Dout_B : in std_logic_vector(0 to 31)
    );
  end component;

  component ilmb_cntlr_3_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component ilmb_cntlr_2_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component ilmb_cntlr_1_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component ilmb_cntlr_0_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component ilmb_3_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component ilmb_2_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component ilmb_1_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component ilmb_0_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component dlmb_cntlr_3_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component dlmb_cntlr_2_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component dlmb_cntlr_1_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component dlmb_cntlr_0_wrapper is
    port (
      LMB_Clk : in std_logic;
      LMB_Rst : in std_logic;
      LMB_ABus : in std_logic_vector(0 to 31);
      LMB_WriteDBus : in std_logic_vector(0 to 31);
      LMB_AddrStrobe : in std_logic;
      LMB_ReadStrobe : in std_logic;
      LMB_WriteStrobe : in std_logic;
      LMB_BE : in std_logic_vector(0 to 3);
      Sl_DBus : out std_logic_vector(0 to 31);
      Sl_Ready : out std_logic;
      BRAM_Rst_A : out std_logic;
      BRAM_Clk_A : out std_logic;
      BRAM_EN_A : out std_logic;
      BRAM_WEN_A : out std_logic_vector(0 to 3);
      BRAM_Addr_A : out std_logic_vector(0 to 31);
      BRAM_Din_A : in std_logic_vector(0 to 31);
      BRAM_Dout_A : out std_logic_vector(0 to 31)
    );
  end component;

  component dlmb_3_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component dlmb_2_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component dlmb_1_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component dlmb_0_wrapper is
    port (
      LMB_Clk : in std_logic;
      SYS_Rst : in std_logic;
      LMB_Rst : out std_logic;
      M_ABus : in std_logic_vector(0 to 31);
      M_ReadStrobe : in std_logic;
      M_WriteStrobe : in std_logic;
      M_AddrStrobe : in std_logic;
      M_DBus : in std_logic_vector(0 to 31);
      M_BE : in std_logic_vector(0 to 3);
      Sl_DBus : in std_logic_vector(0 to 31);
      Sl_Ready : in std_logic_vector(0 to 0);
      LMB_ABus : out std_logic_vector(0 to 31);
      LMB_ReadStrobe : out std_logic;
      LMB_WriteStrobe : out std_logic;
      LMB_AddrStrobe : out std_logic;
      LMB_ReadDBus : out std_logic_vector(0 to 31);
      LMB_WriteDBus : out std_logic_vector(0 to 31);
      LMB_Ready : out std_logic;
      LMB_BE : out std_logic_vector(0 to 3)
    );
  end component;

  component debug_module_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Interrupt : out std_logic;
      Debug_SYS_Rst : out std_logic;
      Debug_Rst : out std_logic;
      Ext_BRK : out std_logic;
      Ext_NM_BRK : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_DBus : in std_logic_vector(0 to 31);
      MDM_DBus : out std_logic_vector(0 to 31);
      MDM_errAck : out std_logic;
      MDM_retry : out std_logic;
      MDM_toutSup : out std_logic;
      MDM_xferAck : out std_logic;
      Dbg_Clk_0 : out std_logic;
      Dbg_TDI_0 : out std_logic;
      Dbg_TDO_0 : in std_logic;
      Dbg_Reg_En_0 : out std_logic_vector(0 to 4);
      Dbg_Capture_0 : out std_logic;
      Dbg_Update_0 : out std_logic;
      Dbg_Clk_1 : out std_logic;
      Dbg_TDI_1 : out std_logic;
      Dbg_TDO_1 : in std_logic;
      Dbg_Reg_En_1 : out std_logic_vector(0 to 4);
      Dbg_Capture_1 : out std_logic;
      Dbg_Update_1 : out std_logic;
      Dbg_Clk_2 : out std_logic;
      Dbg_TDI_2 : out std_logic;
      Dbg_TDO_2 : in std_logic;
      Dbg_Reg_En_2 : out std_logic_vector(0 to 4);
      Dbg_Capture_2 : out std_logic;
      Dbg_Update_2 : out std_logic;
      Dbg_Clk_3 : out std_logic;
      Dbg_TDI_3 : out std_logic;
      Dbg_TDO_3 : in std_logic;
      Dbg_Reg_En_3 : out std_logic_vector(0 to 4);
      Dbg_Capture_3 : out std_logic;
      Dbg_Update_3 : out std_logic;
      Dbg_Clk_4 : out std_logic;
      Dbg_TDI_4 : out std_logic;
      Dbg_TDO_4 : in std_logic;
      Dbg_Reg_En_4 : out std_logic_vector(0 to 4);
      Dbg_Capture_4 : out std_logic;
      Dbg_Update_4 : out std_logic;
      Dbg_Clk_5 : out std_logic;
      Dbg_TDI_5 : out std_logic;
      Dbg_TDO_5 : in std_logic;
      Dbg_Reg_En_5 : out std_logic_vector(0 to 4);
      Dbg_Capture_5 : out std_logic;
      Dbg_Update_5 : out std_logic;
      Dbg_Clk_6 : out std_logic;
      Dbg_TDI_6 : out std_logic;
      Dbg_TDO_6 : in std_logic;
      Dbg_Reg_En_6 : out std_logic_vector(0 to 4);
      Dbg_Capture_6 : out std_logic;
      Dbg_Update_6 : out std_logic;
      Dbg_Clk_7 : out std_logic;
      Dbg_TDI_7 : out std_logic;
      Dbg_TDO_7 : in std_logic;
      Dbg_Reg_En_7 : out std_logic_vector(0 to 4);
      Dbg_Capture_7 : out std_logic;
      Dbg_Update_7 : out std_logic;
      bscan_tdi : out std_logic;
      bscan_reset : out std_logic;
      bscan_shift : out std_logic;
      bscan_update : out std_logic;
      bscan_capture : out std_logic;
      bscan_sel1 : out std_logic;
      bscan_drck1 : out std_logic;
      bscan_tdo1 : in std_logic;
      FSL0_S_CLK : out std_logic;
      FSL0_S_READ : out std_logic;
      FSL0_S_DATA : in std_logic_vector(0 to 31);
      FSL0_S_CONTROL : in std_logic;
      FSL0_S_EXISTS : in std_logic;
      FSL0_M_CLK : out std_logic;
      FSL0_M_WRITE : out std_logic;
      FSL0_M_DATA : out std_logic_vector(0 to 31);
      FSL0_M_CONTROL : out std_logic;
      FSL0_M_FULL : in std_logic
    );
  end component;

  component dcm_0_wrapper is
    port (
      RST : in std_logic;
      CLKIN : in std_logic;
      CLKFB : in std_logic;
      PSEN : in std_logic;
      PSINCDEC : in std_logic;
      PSCLK : in std_logic;
      DSSEN : in std_logic;
      CLK0 : out std_logic;
      CLK90 : out std_logic;
      CLK180 : out std_logic;
      CLK270 : out std_logic;
      CLKDV : out std_logic;
      CLK2X : out std_logic;
      CLK2X180 : out std_logic;
      CLKFX : out std_logic;
      CLKFX180 : out std_logic;
      STATUS : out std_logic_vector(7 downto 0);
      LOCKED : out std_logic;
      PSDONE : out std_logic
    );
  end component;

  component bram_block_3_wrapper is
    port (
      BRAM_Rst_A : in std_logic;
      BRAM_Clk_A : in std_logic;
      BRAM_EN_A : in std_logic;
      BRAM_WEN_A : in std_logic_vector(0 to 3);
      BRAM_Addr_A : in std_logic_vector(0 to 31);
      BRAM_Din_A : out std_logic_vector(0 to 31);
      BRAM_Dout_A : in std_logic_vector(0 to 31);
      BRAM_Rst_B : in std_logic;
      BRAM_Clk_B : in std_logic;
      BRAM_EN_B : in std_logic;
      BRAM_WEN_B : in std_logic_vector(0 to 3);
      BRAM_Addr_B : in std_logic_vector(0 to 31);
      BRAM_Din_B : out std_logic_vector(0 to 31);
      BRAM_Dout_B : in std_logic_vector(0 to 31)
    );
  end component;

  component bram_block_2_wrapper is
    port (
      BRAM_Rst_A : in std_logic;
      BRAM_Clk_A : in std_logic;
      BRAM_EN_A : in std_logic;
      BRAM_WEN_A : in std_logic_vector(0 to 3);
      BRAM_Addr_A : in std_logic_vector(0 to 31);
      BRAM_Din_A : out std_logic_vector(0 to 31);
      BRAM_Dout_A : in std_logic_vector(0 to 31);
      BRAM_Rst_B : in std_logic;
      BRAM_Clk_B : in std_logic;
      BRAM_EN_B : in std_logic;
      BRAM_WEN_B : in std_logic_vector(0 to 3);
      BRAM_Addr_B : in std_logic_vector(0 to 31);
      BRAM_Din_B : out std_logic_vector(0 to 31);
      BRAM_Dout_B : in std_logic_vector(0 to 31)
    );
  end component;

  component bram_block_1_wrapper is
    port (
      BRAM_Rst_A : in std_logic;
      BRAM_Clk_A : in std_logic;
      BRAM_EN_A : in std_logic;
      BRAM_WEN_A : in std_logic_vector(0 to 3);
      BRAM_Addr_A : in std_logic_vector(0 to 31);
      BRAM_Din_A : out std_logic_vector(0 to 31);
      BRAM_Dout_A : in std_logic_vector(0 to 31);
      BRAM_Rst_B : in std_logic;
      BRAM_Clk_B : in std_logic;
      BRAM_EN_B : in std_logic;
      BRAM_WEN_B : in std_logic_vector(0 to 3);
      BRAM_Addr_B : in std_logic_vector(0 to 31);
      BRAM_Din_B : out std_logic_vector(0 to 31);
      BRAM_Dout_B : in std_logic_vector(0 to 31)
    );
  end component;

  component rs232_uart_1_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Interrupt : out std_logic;
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      OPB_DBus : in std_logic_vector(0 to 31);
      UART_DBus : out std_logic_vector(0 to 31);
      UART_errAck : out std_logic;
      UART_retry : out std_logic;
      UART_toutSup : out std_logic;
      UART_xferAck : out std_logic;
      RX : in std_logic;
      TX : out std_logic
    );
  end component;

  component pushbuttons_5bit_wrapper is
    port (
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_Clk : in std_logic;
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_Rst : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      Sln_DBus : out std_logic_vector(0 to 31);
      Sln_errAck : out std_logic;
      Sln_retry : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_xferAck : out std_logic;
      IP2INTC_Irpt : out std_logic;
      GPIO_in : in std_logic_vector(0 to 4);
      GPIO_d_out : out std_logic_vector(0 to 4);
      GPIO_t_out : out std_logic_vector(0 to 4);
      GPIO2_in : in std_logic_vector(0 to 4);
      GPIO2_d_out : out std_logic_vector(0 to 4);
      GPIO2_t_out : out std_logic_vector(0 to 4);
      GPIO_IO_I : in std_logic_vector(0 to 4);
      GPIO_IO_O : out std_logic_vector(0 to 4);
      GPIO_IO_T : out std_logic_vector(0 to 4);
      GPIO2_IO_I : in std_logic_vector(0 to 4);
      GPIO2_IO_O : out std_logic_vector(0 to 4);
      GPIO2_IO_T : out std_logic_vector(0 to 4)
    );
  end component;

  component p3_opb_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : out std_logic;
      SYS_Rst : in std_logic;
      Debug_SYS_Rst : in std_logic;
      WDT_Rst : in std_logic;
      M_ABus : in std_logic_vector(0 to 63);
      M_BE : in std_logic_vector(0 to 7);
      M_beXfer : in std_logic_vector(0 to 1);
      M_busLock : in std_logic_vector(0 to 1);
      M_DBus : in std_logic_vector(0 to 63);
      M_DBusEn : in std_logic_vector(0 to 1);
      M_DBusEn32_63 : in std_logic_vector(0 to 1);
      M_dwXfer : in std_logic_vector(0 to 1);
      M_fwXfer : in std_logic_vector(0 to 1);
      M_hwXfer : in std_logic_vector(0 to 1);
      M_request : in std_logic_vector(0 to 1);
      M_RNW : in std_logic_vector(0 to 1);
      M_select : in std_logic_vector(0 to 1);
      M_seqAddr : in std_logic_vector(0 to 1);
      Sl_beAck : in std_logic_vector(0 to 1);
      Sl_DBus : in std_logic_vector(0 to 63);
      Sl_DBusEn : in std_logic_vector(0 to 1);
      Sl_DBusEn32_63 : in std_logic_vector(0 to 1);
      Sl_errAck : in std_logic_vector(0 to 1);
      Sl_dwAck : in std_logic_vector(0 to 1);
      Sl_fwAck : in std_logic_vector(0 to 1);
      Sl_hwAck : in std_logic_vector(0 to 1);
      Sl_retry : in std_logic_vector(0 to 1);
      Sl_toutSup : in std_logic_vector(0 to 1);
      Sl_xferAck : in std_logic_vector(0 to 1);
      OPB_MRequest : out std_logic_vector(0 to 1);
      OPB_ABus : out std_logic_vector(0 to 31);
      OPB_BE : out std_logic_vector(0 to 3);
      OPB_beXfer : out std_logic;
      OPB_beAck : out std_logic;
      OPB_busLock : out std_logic;
      OPB_rdDBus : out std_logic_vector(0 to 31);
      OPB_wrDBus : out std_logic_vector(0 to 31);
      OPB_DBus : out std_logic_vector(0 to 31);
      OPB_errAck : out std_logic;
      OPB_dwAck : out std_logic;
      OPB_dwXfer : out std_logic;
      OPB_fwAck : out std_logic;
      OPB_fwXfer : out std_logic;
      OPB_hwAck : out std_logic;
      OPB_hwXfer : out std_logic;
      OPB_MGrant : out std_logic_vector(0 to 1);
      OPB_pendReq : out std_logic_vector(0 to 1);
      OPB_retry : out std_logic;
      OPB_RNW : out std_logic;
      OPB_select : out std_logic;
      OPB_seqAddr : out std_logic;
      OPB_timeout : out std_logic;
      OPB_toutSup : out std_logic;
      OPB_xferAck : out std_logic
    );
  end component;

  component p2_opb_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : out std_logic;
      SYS_Rst : in std_logic;
      Debug_SYS_Rst : in std_logic;
      WDT_Rst : in std_logic;
      M_ABus : in std_logic_vector(0 to 63);
      M_BE : in std_logic_vector(0 to 7);
      M_beXfer : in std_logic_vector(0 to 1);
      M_busLock : in std_logic_vector(0 to 1);
      M_DBus : in std_logic_vector(0 to 63);
      M_DBusEn : in std_logic_vector(0 to 1);
      M_DBusEn32_63 : in std_logic_vector(0 to 1);
      M_dwXfer : in std_logic_vector(0 to 1);
      M_fwXfer : in std_logic_vector(0 to 1);
      M_hwXfer : in std_logic_vector(0 to 1);
      M_request : in std_logic_vector(0 to 1);
      M_RNW : in std_logic_vector(0 to 1);
      M_select : in std_logic_vector(0 to 1);
      M_seqAddr : in std_logic_vector(0 to 1);
      Sl_beAck : in std_logic_vector(0 to 1);
      Sl_DBus : in std_logic_vector(0 to 63);
      Sl_DBusEn : in std_logic_vector(0 to 1);
      Sl_DBusEn32_63 : in std_logic_vector(0 to 1);
      Sl_errAck : in std_logic_vector(0 to 1);
      Sl_dwAck : in std_logic_vector(0 to 1);
      Sl_fwAck : in std_logic_vector(0 to 1);
      Sl_hwAck : in std_logic_vector(0 to 1);
      Sl_retry : in std_logic_vector(0 to 1);
      Sl_toutSup : in std_logic_vector(0 to 1);
      Sl_xferAck : in std_logic_vector(0 to 1);
      OPB_MRequest : out std_logic_vector(0 to 1);
      OPB_ABus : out std_logic_vector(0 to 31);
      OPB_BE : out std_logic_vector(0 to 3);
      OPB_beXfer : out std_logic;
      OPB_beAck : out std_logic;
      OPB_busLock : out std_logic;
      OPB_rdDBus : out std_logic_vector(0 to 31);
      OPB_wrDBus : out std_logic_vector(0 to 31);
      OPB_DBus : out std_logic_vector(0 to 31);
      OPB_errAck : out std_logic;
      OPB_dwAck : out std_logic;
      OPB_dwXfer : out std_logic;
      OPB_fwAck : out std_logic;
      OPB_fwXfer : out std_logic;
      OPB_hwAck : out std_logic;
      OPB_hwXfer : out std_logic;
      OPB_MGrant : out std_logic_vector(0 to 1);
      OPB_pendReq : out std_logic_vector(0 to 1);
      OPB_retry : out std_logic;
      OPB_RNW : out std_logic;
      OPB_select : out std_logic;
      OPB_seqAddr : out std_logic;
      OPB_timeout : out std_logic;
      OPB_toutSup : out std_logic;
      OPB_xferAck : out std_logic
    );
  end component;

  component p1_opb_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : out std_logic;
      SYS_Rst : in std_logic;
      Debug_SYS_Rst : in std_logic;
      WDT_Rst : in std_logic;
      M_ABus : in std_logic_vector(0 to 63);
      M_BE : in std_logic_vector(0 to 7);
      M_beXfer : in std_logic_vector(0 to 1);
      M_busLock : in std_logic_vector(0 to 1);
      M_DBus : in std_logic_vector(0 to 63);
      M_DBusEn : in std_logic_vector(0 to 1);
      M_DBusEn32_63 : in std_logic_vector(0 to 1);
      M_dwXfer : in std_logic_vector(0 to 1);
      M_fwXfer : in std_logic_vector(0 to 1);
      M_hwXfer : in std_logic_vector(0 to 1);
      M_request : in std_logic_vector(0 to 1);
      M_RNW : in std_logic_vector(0 to 1);
      M_select : in std_logic_vector(0 to 1);
      M_seqAddr : in std_logic_vector(0 to 1);
      Sl_beAck : in std_logic_vector(0 to 1);
      Sl_DBus : in std_logic_vector(0 to 63);
      Sl_DBusEn : in std_logic_vector(0 to 1);
      Sl_DBusEn32_63 : in std_logic_vector(0 to 1);
      Sl_errAck : in std_logic_vector(0 to 1);
      Sl_dwAck : in std_logic_vector(0 to 1);
      Sl_fwAck : in std_logic_vector(0 to 1);
      Sl_hwAck : in std_logic_vector(0 to 1);
      Sl_retry : in std_logic_vector(0 to 1);
      Sl_toutSup : in std_logic_vector(0 to 1);
      Sl_xferAck : in std_logic_vector(0 to 1);
      OPB_MRequest : out std_logic_vector(0 to 1);
      OPB_ABus : out std_logic_vector(0 to 31);
      OPB_BE : out std_logic_vector(0 to 3);
      OPB_beXfer : out std_logic;
      OPB_beAck : out std_logic;
      OPB_busLock : out std_logic;
      OPB_rdDBus : out std_logic_vector(0 to 31);
      OPB_wrDBus : out std_logic_vector(0 to 31);
      OPB_DBus : out std_logic_vector(0 to 31);
      OPB_errAck : out std_logic;
      OPB_dwAck : out std_logic;
      OPB_dwXfer : out std_logic;
      OPB_fwAck : out std_logic;
      OPB_fwXfer : out std_logic;
      OPB_hwAck : out std_logic;
      OPB_hwXfer : out std_logic;
      OPB_MGrant : out std_logic_vector(0 to 1);
      OPB_pendReq : out std_logic_vector(0 to 1);
      OPB_retry : out std_logic;
      OPB_RNW : out std_logic;
      OPB_select : out std_logic;
      OPB_seqAddr : out std_logic;
      OPB_timeout : out std_logic;
      OPB_toutSup : out std_logic;
      OPB_xferAck : out std_logic
    );
  end component;

  component p0_opb_wrapper is
    port (
      OPB_Clk : in std_logic;
      OPB_Rst : out std_logic;
      SYS_Rst : in std_logic;
      Debug_SYS_Rst : in std_logic;
      WDT_Rst : in std_logic;
      M_ABus : in std_logic_vector(0 to 63);
      M_BE : in std_logic_vector(0 to 7);
      M_beXfer : in std_logic_vector(0 to 1);
      M_busLock : in std_logic_vector(0 to 1);
      M_DBus : in std_logic_vector(0 to 63);
      M_DBusEn : in std_logic_vector(0 to 1);
      M_DBusEn32_63 : in std_logic_vector(0 to 1);
      M_dwXfer : in std_logic_vector(0 to 1);
      M_fwXfer : in std_logic_vector(0 to 1);
      M_hwXfer : in std_logic_vector(0 to 1);
      M_request : in std_logic_vector(0 to 1);
      M_RNW : in std_logic_vector(0 to 1);
      M_select : in std_logic_vector(0 to 1);
      M_seqAddr : in std_logic_vector(0 to 1);
      Sl_beAck : in std_logic_vector(0 to 7);
      Sl_DBus : in std_logic_vector(0 to 255);
      Sl_DBusEn : in std_logic_vector(0 to 7);
      Sl_DBusEn32_63 : in std_logic_vector(0 to 7);
      Sl_errAck : in std_logic_vector(0 to 7);
      Sl_dwAck : in std_logic_vector(0 to 7);
      Sl_fwAck : in std_logic_vector(0 to 7);
      Sl_hwAck : in std_logic_vector(0 to 7);
      Sl_retry : in std_logic_vector(0 to 7);
      Sl_toutSup : in std_logic_vector(0 to 7);
      Sl_xferAck : in std_logic_vector(0 to 7);
      OPB_MRequest : out std_logic_vector(0 to 1);
      OPB_ABus : out std_logic_vector(0 to 31);
      OPB_BE : out std_logic_vector(0 to 3);
      OPB_beXfer : out std_logic;
      OPB_beAck : out std_logic;
      OPB_busLock : out std_logic;
      OPB_rdDBus : out std_logic_vector(0 to 31);
      OPB_wrDBus : out std_logic_vector(0 to 31);
      OPB_DBus : out std_logic_vector(0 to 31);
      OPB_errAck : out std_logic;
      OPB_dwAck : out std_logic;
      OPB_dwXfer : out std_logic;
      OPB_fwAck : out std_logic;
      OPB_fwXfer : out std_logic;
      OPB_hwAck : out std_logic;
      OPB_hwXfer : out std_logic;
      OPB_MGrant : out std_logic_vector(0 to 1);
      OPB_pendReq : out std_logic_vector(0 to 1);
      OPB_retry : out std_logic;
      OPB_RNW : out std_logic;
      OPB_select : out std_logic;
      OPB_seqAddr : out std_logic;
      OPB_timeout : out std_logic;
      OPB_toutSup : out std_logic;
      OPB_xferAck : out std_logic
    );
  end component;

  component leds_4bit_wrapper is
    port (
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_Clk : in std_logic;
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_Rst : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      Sln_DBus : out std_logic_vector(0 to 31);
      Sln_errAck : out std_logic;
      Sln_retry : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_xferAck : out std_logic;
      IP2INTC_Irpt : out std_logic;
      GPIO_in : in std_logic_vector(0 to 3);
      GPIO_d_out : out std_logic_vector(0 to 3);
      GPIO_t_out : out std_logic_vector(0 to 3);
      GPIO2_in : in std_logic_vector(0 to 3);
      GPIO2_d_out : out std_logic_vector(0 to 3);
      GPIO2_t_out : out std_logic_vector(0 to 3);
      GPIO_IO_I : in std_logic_vector(0 to 3);
      GPIO_IO_O : out std_logic_vector(0 to 3);
      GPIO_IO_T : out std_logic_vector(0 to 3);
      GPIO2_IO_I : in std_logic_vector(0 to 3);
      GPIO2_IO_O : out std_logic_vector(0 to 3);
      GPIO2_IO_T : out std_logic_vector(0 to 3)
    );
  end component;

  component dipsws_4bit_wrapper is
    port (
      OPB_ABus : in std_logic_vector(0 to 31);
      OPB_BE : in std_logic_vector(0 to 3);
      OPB_Clk : in std_logic;
      OPB_DBus : in std_logic_vector(0 to 31);
      OPB_RNW : in std_logic;
      OPB_Rst : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic;
      Sln_DBus : out std_logic_vector(0 to 31);
      Sln_errAck : out std_logic;
      Sln_retry : out std_logic;
      Sln_toutSup : out std_logic;
      Sln_xferAck : out std_logic;
      IP2INTC_Irpt : out std_logic;
      GPIO_in : in std_logic_vector(0 to 3);
      GPIO_d_out : out std_logic_vector(0 to 3);
      GPIO_t_out : out std_logic_vector(0 to 3);
      GPIO2_in : in std_logic_vector(0 to 3);
      GPIO2_d_out : out std_logic_vector(0 to 3);
      GPIO2_t_out : out std_logic_vector(0 to 3);
      GPIO_IO_I : in std_logic_vector(0 to 3);
      GPIO_IO_O : out std_logic_vector(0 to 3);
      GPIO_IO_T : out std_logic_vector(0 to 3);
      GPIO2_IO_I : in std_logic_vector(0 to 3);
      GPIO2_IO_O : out std_logic_vector(0 to 3);
      GPIO2_IO_T : out std_logic_vector(0 to 3)
    );
  end component;

  component IOBUF is
    port (
      I : in std_logic;
      IO : inout std_logic;
      O : out std_logic;
      T : in std_logic
    );
  end component;

  -- Internal signals

  signal DBG_CAPTURE_s : std_logic;
  signal DBG_CLK_s : std_logic;
  signal DBG_REG_EN_s : std_logic_vector(0 to 4);
  signal DBG_TDI_s : std_logic;
  signal DBG_TDO_s : std_logic;
  signal DBG_UPDATE_s : std_logic;
  signal Debug_Rst : std_logic;
  signal Ext_BRK : std_logic;
  signal Ext_NM_BRK : std_logic;
  signal P0_opb_Debug_SYS_Rst : std_logic;
  signal P0_opb_M_ABus : std_logic_vector(0 to 63);
  signal P0_opb_M_BE : std_logic_vector(0 to 7);
  signal P0_opb_M_DBus : std_logic_vector(0 to 63);
  signal P0_opb_M_RNW : std_logic_vector(0 to 1);
  signal P0_opb_M_busLock : std_logic_vector(0 to 1);
  signal P0_opb_M_request : std_logic_vector(0 to 1);
  signal P0_opb_M_select : std_logic_vector(0 to 1);
  signal P0_opb_M_seqAddr : std_logic_vector(0 to 1);
  signal P0_opb_OPB_ABus : std_logic_vector(0 to 31);
  signal P0_opb_OPB_BE : std_logic_vector(0 to 3);
  signal P0_opb_OPB_DBus : std_logic_vector(0 to 31);
  signal P0_opb_OPB_MGrant : std_logic_vector(0 to 1);
  signal P0_opb_OPB_RNW : std_logic;
  signal P0_opb_OPB_Rst : std_logic;
  signal P0_opb_OPB_errAck : std_logic;
  signal P0_opb_OPB_retry : std_logic;
  signal P0_opb_OPB_select : std_logic;
  signal P0_opb_OPB_seqAddr : std_logic;
  signal P0_opb_OPB_timeout : std_logic;
  signal P0_opb_OPB_xferAck : std_logic;
  signal P0_opb_Sl_DBus : std_logic_vector(0 to 255);
  signal P0_opb_Sl_errAck : std_logic_vector(0 to 7);
  signal P0_opb_Sl_retry : std_logic_vector(0 to 7);
  signal P0_opb_Sl_toutSup : std_logic_vector(0 to 7);
  signal P0_opb_Sl_xferAck : std_logic_vector(0 to 7);
  signal P1_opb_M_ABus : std_logic_vector(0 to 63);
  signal P1_opb_M_BE : std_logic_vector(0 to 7);
  signal P1_opb_M_DBus : std_logic_vector(0 to 63);
  signal P1_opb_M_RNW : std_logic_vector(0 to 1);
  signal P1_opb_M_busLock : std_logic_vector(0 to 1);
  signal P1_opb_M_request : std_logic_vector(0 to 1);
  signal P1_opb_M_select : std_logic_vector(0 to 1);
  signal P1_opb_M_seqAddr : std_logic_vector(0 to 1);
  signal P1_opb_OPB_ABus : std_logic_vector(0 to 31);
  signal P1_opb_OPB_BE : std_logic_vector(0 to 3);
  signal P1_opb_OPB_DBus : std_logic_vector(0 to 31);
  signal P1_opb_OPB_MGrant : std_logic_vector(0 to 1);
  signal P1_opb_OPB_RNW : std_logic;
  signal P1_opb_OPB_Rst : std_logic;
  signal P1_opb_OPB_errAck : std_logic;
  signal P1_opb_OPB_retry : std_logic;
  signal P1_opb_OPB_select : std_logic;
  signal P1_opb_OPB_seqAddr : std_logic;
  signal P1_opb_OPB_timeout : std_logic;
  signal P1_opb_OPB_xferAck : std_logic;
  signal P1_opb_Sl_DBus : std_logic_vector(0 to 63);
  signal P1_opb_Sl_errAck : std_logic_vector(0 to 1);
  signal P1_opb_Sl_retry : std_logic_vector(0 to 1);
  signal P1_opb_Sl_toutSup : std_logic_vector(0 to 1);
  signal P1_opb_Sl_xferAck : std_logic_vector(0 to 1);
  signal P2_opb_M_ABus : std_logic_vector(0 to 63);
  signal P2_opb_M_BE : std_logic_vector(0 to 7);
  signal P2_opb_M_DBus : std_logic_vector(0 to 63);
  signal P2_opb_M_RNW : std_logic_vector(0 to 1);
  signal P2_opb_M_busLock : std_logic_vector(0 to 1);
  signal P2_opb_M_request : std_logic_vector(0 to 1);
  signal P2_opb_M_select : std_logic_vector(0 to 1);
  signal P2_opb_M_seqAddr : std_logic_vector(0 to 1);
  signal P2_opb_OPB_ABus : std_logic_vector(0 to 31);
  signal P2_opb_OPB_BE : std_logic_vector(0 to 3);
  signal P2_opb_OPB_DBus : std_logic_vector(0 to 31);
  signal P2_opb_OPB_MGrant : std_logic_vector(0 to 1);
  signal P2_opb_OPB_RNW : std_logic;
  signal P2_opb_OPB_Rst : std_logic;
  signal P2_opb_OPB_errAck : std_logic;
  signal P2_opb_OPB_retry : std_logic;
  signal P2_opb_OPB_select : std_logic;
  signal P2_opb_OPB_seqAddr : std_logic;
  signal P2_opb_OPB_timeout : std_logic;
  signal P2_opb_OPB_xferAck : std_logic;
  signal P2_opb_Sl_DBus : std_logic_vector(0 to 63);
  signal P2_opb_Sl_errAck : std_logic_vector(0 to 1);
  signal P2_opb_Sl_retry : std_logic_vector(0 to 1);
  signal P2_opb_Sl_toutSup : std_logic_vector(0 to 1);
  signal P2_opb_Sl_xferAck : std_logic_vector(0 to 1);
  signal P3_opb_M_ABus : std_logic_vector(0 to 63);
  signal P3_opb_M_BE : std_logic_vector(0 to 7);
  signal P3_opb_M_DBus : std_logic_vector(0 to 63);
  signal P3_opb_M_RNW : std_logic_vector(0 to 1);
  signal P3_opb_M_busLock : std_logic_vector(0 to 1);
  signal P3_opb_M_request : std_logic_vector(0 to 1);
  signal P3_opb_M_select : std_logic_vector(0 to 1);
  signal P3_opb_M_seqAddr : std_logic_vector(0 to 1);
  signal P3_opb_OPB_ABus : std_logic_vector(0 to 31);
  signal P3_opb_OPB_BE : std_logic_vector(0 to 3);
  signal P3_opb_OPB_DBus : std_logic_vector(0 to 31);
  signal P3_opb_OPB_MGrant : std_logic_vector(0 to 1);
  signal P3_opb_OPB_RNW : std_logic;
  signal P3_opb_OPB_Rst : std_logic;
  signal P3_opb_OPB_errAck : std_logic;
  signal P3_opb_OPB_retry : std_logic;
  signal P3_opb_OPB_select : std_logic;
  signal P3_opb_OPB_seqAddr : std_logic;
  signal P3_opb_OPB_timeout : std_logic;
  signal P3_opb_OPB_xferAck : std_logic;
  signal P3_opb_Sl_DBus : std_logic_vector(0 to 63);
  signal P3_opb_Sl_errAck : std_logic_vector(0 to 1);
  signal P3_opb_Sl_retry : std_logic_vector(0 to 1);
  signal P3_opb_Sl_toutSup : std_logic_vector(0 to 1);
  signal P3_opb_Sl_xferAck : std_logic_vector(0 to 1);
  signal dcm_clk_s : std_logic;
  signal dlmb_0_LMB_ABus : std_logic_vector(0 to 31);
  signal dlmb_0_LMB_AddrStrobe : std_logic;
  signal dlmb_0_LMB_BE : std_logic_vector(0 to 3);
  signal dlmb_0_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal dlmb_0_LMB_ReadStrobe : std_logic;
  signal dlmb_0_LMB_Ready : std_logic;
  signal dlmb_0_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal dlmb_0_LMB_WriteStrobe : std_logic;
  signal dlmb_0_M_ABus : std_logic_vector(0 to 31);
  signal dlmb_0_M_AddrStrobe : std_logic;
  signal dlmb_0_M_BE : std_logic_vector(0 to 3);
  signal dlmb_0_M_DBus : std_logic_vector(0 to 31);
  signal dlmb_0_M_ReadStrobe : std_logic;
  signal dlmb_0_M_WriteStrobe : std_logic;
  signal dlmb_0_OPB_Rst : std_logic;
  signal dlmb_0_Sl_DBus : std_logic_vector(0 to 31);
  signal dlmb_0_Sl_Ready : std_logic_vector(0 to 0);
  signal dlmb_1_LMB_ABus : std_logic_vector(0 to 31);
  signal dlmb_1_LMB_AddrStrobe : std_logic;
  signal dlmb_1_LMB_BE : std_logic_vector(0 to 3);
  signal dlmb_1_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal dlmb_1_LMB_ReadStrobe : std_logic;
  signal dlmb_1_LMB_Ready : std_logic;
  signal dlmb_1_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal dlmb_1_LMB_WriteStrobe : std_logic;
  signal dlmb_1_M_ABus : std_logic_vector(0 to 31);
  signal dlmb_1_M_AddrStrobe : std_logic;
  signal dlmb_1_M_BE : std_logic_vector(0 to 3);
  signal dlmb_1_M_DBus : std_logic_vector(0 to 31);
  signal dlmb_1_M_ReadStrobe : std_logic;
  signal dlmb_1_M_WriteStrobe : std_logic;
  signal dlmb_1_OPB_Rst : std_logic;
  signal dlmb_1_Sl_DBus : std_logic_vector(0 to 31);
  signal dlmb_1_Sl_Ready : std_logic_vector(0 to 0);
  signal dlmb_2_LMB_ABus : std_logic_vector(0 to 31);
  signal dlmb_2_LMB_AddrStrobe : std_logic;
  signal dlmb_2_LMB_BE : std_logic_vector(0 to 3);
  signal dlmb_2_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal dlmb_2_LMB_ReadStrobe : std_logic;
  signal dlmb_2_LMB_Ready : std_logic;
  signal dlmb_2_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal dlmb_2_LMB_WriteStrobe : std_logic;
  signal dlmb_2_M_ABus : std_logic_vector(0 to 31);
  signal dlmb_2_M_AddrStrobe : std_logic;
  signal dlmb_2_M_BE : std_logic_vector(0 to 3);
  signal dlmb_2_M_DBus : std_logic_vector(0 to 31);
  signal dlmb_2_M_ReadStrobe : std_logic;
  signal dlmb_2_M_WriteStrobe : std_logic;
  signal dlmb_2_OPB_Rst : std_logic;
  signal dlmb_2_Sl_DBus : std_logic_vector(0 to 31);
  signal dlmb_2_Sl_Ready : std_logic_vector(0 to 0);
  signal dlmb_3_LMB_ABus : std_logic_vector(0 to 31);
  signal dlmb_3_LMB_AddrStrobe : std_logic;
  signal dlmb_3_LMB_BE : std_logic_vector(0 to 3);
  signal dlmb_3_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal dlmb_3_LMB_ReadStrobe : std_logic;
  signal dlmb_3_LMB_Ready : std_logic;
  signal dlmb_3_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal dlmb_3_LMB_WriteStrobe : std_logic;
  signal dlmb_3_M_ABus : std_logic_vector(0 to 31);
  signal dlmb_3_M_AddrStrobe : std_logic;
  signal dlmb_3_M_BE : std_logic_vector(0 to 3);
  signal dlmb_3_M_DBus : std_logic_vector(0 to 31);
  signal dlmb_3_M_ReadStrobe : std_logic;
  signal dlmb_3_M_WriteStrobe : std_logic;
  signal dlmb_3_OPB_Rst : std_logic;
  signal dlmb_3_Sl_DBus : std_logic_vector(0 to 31);
  signal dlmb_3_Sl_Ready : std_logic_vector(0 to 0);
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_Clk : std_logic;
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_EN : std_logic;
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_Rst : std_logic;
  signal dlmb_cntlr_1_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_Clk : std_logic;
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_EN : std_logic;
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_Rst : std_logic;
  signal dlmb_cntlr_2_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_Clk : std_logic;
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_EN : std_logic;
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_Rst : std_logic;
  signal dlmb_cntlr_3_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31);
  signal dlmb_port_BRAM_Clk : std_logic;
  signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31);
  signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31);
  signal dlmb_port_BRAM_EN : std_logic;
  signal dlmb_port_BRAM_Rst : std_logic;
  signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3);
  signal fpga_0_DIPSWs_4Bit_GPIO_IO_I : std_logic_vector(0 to 3);
  signal fpga_0_DIPSWs_4Bit_GPIO_IO_O : std_logic_vector(0 to 3);
  signal fpga_0_DIPSWs_4Bit_GPIO_IO_T : std_logic_vector(0 to 3);
  signal fpga_0_LEDs_4Bit_GPIO_IO_I : std_logic_vector(0 to 3);
  signal fpga_0_LEDs_4Bit_GPIO_IO_O : std_logic_vector(0 to 3);
  signal fpga_0_LEDs_4Bit_GPIO_IO_T : std_logic_vector(0 to 3);
  signal fpga_0_PushButtons_5Bit_GPIO_IO_I : std_logic_vector(0 to 4);
  signal fpga_0_PushButtons_5Bit_GPIO_IO_O : std_logic_vector(0 to 4);
  signal fpga_0_PushButtons_5Bit_GPIO_IO_T : std_logic_vector(0 to 4);
  signal fpga_0_RS232_Uart_1_RX : std_logic;
  signal fpga_0_RS232_Uart_1_TX : std_logic;
  signal ilmb_0_LMB_ABus : std_logic_vector(0 to 31);
  signal ilmb_0_LMB_AddrStrobe : std_logic;
  signal ilmb_0_LMB_BE : std_logic_vector(0 to 3);
  signal ilmb_0_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal ilmb_0_LMB_ReadStrobe : std_logic;
  signal ilmb_0_LMB_Ready : std_logic;
  signal ilmb_0_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal ilmb_0_LMB_WriteStrobe : std_logic;
  signal ilmb_0_M_ABus : std_logic_vector(0 to 31);
  signal ilmb_0_M_AddrStrobe : std_logic;
  signal ilmb_0_M_ReadStrobe : std_logic;
  signal ilmb_0_OPB_Rst : std_logic;
  signal ilmb_0_Sl_DBus : std_logic_vector(0 to 31);
  signal ilmb_0_Sl_Ready : std_logic_vector(0 to 0);
  signal ilmb_1_LMB_ABus : std_logic_vector(0 to 31);
  signal ilmb_1_LMB_AddrStrobe : std_logic;
  signal ilmb_1_LMB_BE : std_logic_vector(0 to 3);
  signal ilmb_1_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal ilmb_1_LMB_ReadStrobe : std_logic;
  signal ilmb_1_LMB_Ready : std_logic;
  signal ilmb_1_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal ilmb_1_LMB_WriteStrobe : std_logic;
  signal ilmb_1_M_ABus : std_logic_vector(0 to 31);
  signal ilmb_1_M_AddrStrobe : std_logic;
  signal ilmb_1_M_ReadStrobe : std_logic;
  signal ilmb_1_OPB_Rst : std_logic;
  signal ilmb_1_Sl_DBus : std_logic_vector(0 to 31);
  signal ilmb_1_Sl_Ready : std_logic_vector(0 to 0);
  signal ilmb_2_LMB_ABus : std_logic_vector(0 to 31);
  signal ilmb_2_LMB_AddrStrobe : std_logic;
  signal ilmb_2_LMB_BE : std_logic_vector(0 to 3);
  signal ilmb_2_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal ilmb_2_LMB_ReadStrobe : std_logic;
  signal ilmb_2_LMB_Ready : std_logic;
  signal ilmb_2_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal ilmb_2_LMB_WriteStrobe : std_logic;
  signal ilmb_2_M_ABus : std_logic_vector(0 to 31);
  signal ilmb_2_M_AddrStrobe : std_logic;
  signal ilmb_2_M_ReadStrobe : std_logic;
  signal ilmb_2_OPB_Rst : std_logic;
  signal ilmb_2_Sl_DBus : std_logic_vector(0 to 31);
  signal ilmb_2_Sl_Ready : std_logic_vector(0 to 0);
  signal ilmb_3_LMB_ABus : std_logic_vector(0 to 31);
  signal ilmb_3_LMB_AddrStrobe : std_logic;
  signal ilmb_3_LMB_BE : std_logic_vector(0 to 3);
  signal ilmb_3_LMB_ReadDBus : std_logic_vector(0 to 31);
  signal ilmb_3_LMB_ReadStrobe : std_logic;
  signal ilmb_3_LMB_Ready : std_logic;
  signal ilmb_3_LMB_WriteDBus : std_logic_vector(0 to 31);
  signal ilmb_3_LMB_WriteStrobe : std_logic;
  signal ilmb_3_M_ABus : std_logic_vector(0 to 31);
  signal ilmb_3_M_AddrStrobe : std_logic;
  signal ilmb_3_M_ReadStrobe : std_logic;
  signal ilmb_3_OPB_Rst : std_logic;
  signal ilmb_3_Sl_DBus : std_logic_vector(0 to 31);
  signal ilmb_3_Sl_Ready : std_logic_vector(0 to 0);
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_Clk : std_logic;
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_EN : std_logic;
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_Rst : std_logic;
  signal ilmb_cntlr_1_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_Clk : std_logic;
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_EN : std_logic;
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_Rst : std_logic;
  signal ilmb_cntlr_2_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_Addr : std_logic_vector(0 to 31);
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_Clk : std_logic;
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_Din : std_logic_vector(0 to 31);
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_Dout : std_logic_vector(0 to 31);
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_EN : std_logic;
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_Rst : std_logic;
  signal ilmb_cntlr_3_BRAM_PORT_BRAM_WEN : std_logic_vector(0 to 3);
  signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31);
  signal ilmb_port_BRAM_Clk : std_logic;
  signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31);
  signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31);
  signal ilmb_port_BRAM_EN : std_logic;
  signal ilmb_port_BRAM_Rst : std_logic;
  signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3);
  signal net_gnd0 : std_logic;
  signal net_gnd2 : std_logic_vector(0 to 1);
  signal net_gnd4 : std_logic_vector(0 to 3);
  signal net_gnd5 : std_logic_vector(0 to 4);
  signal net_gnd8 : std_logic_vector(0 to 7);
  signal net_gnd32 : std_logic_vector(0 to 31);
  signal net_vcc2 : std_logic_vector(0 to 1);
  signal net_vcc8 : std_logic_vector(0 to 7);
  signal shared_mem_if_0_External_Mem_Ack_in : std_logic;
  signal shared_mem_if_0_External_Mem_Ack_out : std_logic;
  signal shared_mem_if_0_External_Mem_Addr : std_logic_vector(12 downto 0);
  signal shared_mem_if_0_External_Mem_Data_In : std_logic_vector(15 downto 0);
  signal shared_mem_if_0_External_Mem_Data_Out : std_logic_vector(15 downto 0);
  signal shared_mem_if_0_External_Mem_RD_WR : std_logic;
  signal shared_mem_if_0_External_Mem_Request : std_logic;
  signal shared_mem_if_1_External_Mem_Ack_in : std_logic;
  signal shared_mem_if_1_External_Mem_Ack_out : std_logic;
  signal shared_mem_if_1_External_Mem_Addr : std_logic_vector(12 downto 0);
  signal shared_mem_if_1_External_Mem_Data_In : std_logic_vector(15 downto 0);
  signal shared_mem_if_1_External_Mem_Data_Out : std_logic_vector(15 downto 0);
  signal shared_mem_if_1_External_Mem_RD_WR : std_logic;
  signal shared_mem_if_1_External_Mem_Request : std_logic;
  signal shared_mem_if_2_External_Mem_Ack_in : std_logic;
  signal shared_mem_if_2_External_Mem_Ack_out : std_logic;
  signal shared_mem_if_2_External_Mem_Addr : std_logic_vector(12 downto 0);
  signal shared_mem_if_2_External_Mem_Data_In : std_logic_vector(15 downto 0);
  signal shared_mem_if_2_External_Mem_Data_Out : std_logic_vector(15 downto 0);
  signal shared_mem_if_2_External_Mem_RD_WR : std_logic;
  signal shared_mem_if_2_External_Mem_Request : std_logic;
  signal shared_mem_if_3_External_Mem_Ack_in : std_logic;
  signal shared_mem_if_3_External_Mem_Ack_out : std_logic;
  signal shared_mem_if_3_External_Mem_Addr : std_logic_vector(12 downto 0);
  signal shared_mem_if_3_External_Mem_Data_In : std_logic_vector(15 downto 0);
  signal shared_mem_if_3_External_Mem_Data_Out : std_logic_vector(15 downto 0);
  signal shared_mem_if_3_External_Mem_RD_WR : std_logic;
  signal shared_mem_if_3_External_Mem_Request : std_logic;
  signal snoopy_if_0_data : std_logic_vector(31 downto 0);
  signal snoopy_if_0_info_addr : std_logic_vector(3 downto 0);
  signal snoopy_if_0_proc_task_addr : std_logic_vector(3 downto 0);
  signal sys_clk_s : std_logic;
  signal sys_rst_s : std_logic;
  signal task_controller_if_0_all_procs_done : std_logic;
  signal task_controller_if_0_dfg_node : std_logic_vector(7 downto 0);
  signal task_controller_if_0_executing : std_logic;
  signal task_controller_if_0_iteration_num : std_logic_vector(15 downto 0);
  signal task_controller_if_0_proc_done : std_logic;
  signal task_controller_if_0_start_exec : std_logic;
  signal task_controller_if_0_start_task_control : std_logic;
  signal task_controller_if_1_all_procs_done : std_logic;
  signal task_controller_if_1_dfg_node : std_logic_vector(7 downto 0);
  signal task_controller_if_1_executing : std_logic;
  signal task_controller_if_1_iteration_num : std_logic_vector(15 downto 0);
  signal task_controller_if_1_proc_done : std_logic;
  signal task_controller_if_1_start_exec : std_logic;
  signal task_controller_if_2_all_procs_done : std_logic;
  signal task_controller_if_2_dfg_node : std_logic_vector(7 downto 0);
  signal task_controller_if_2_executing : std_logic;
  signal task_controller_if_2_iteration_num : std_logic_vector(15 downto 0);
  signal task_controller_if_2_proc_done : std_logic;
  signal task_controller_if_2_start_exec : std_logic;
  signal task_controller_if_3_all_procs_done : std_logic;
  signal task_controller_if_3_dfg_node : std_logic_vector(7 downto 0);
  signal task_controller_if_3_executing : std_logic;
  signal task_controller_if_3_iteration_num : std_logic_vector(15 downto 0);
  signal task_controller_if_3_proc_done : std_logic;
  signal task_controller_if_3_start_exec : std_logic;

  attribute BOX_TYPE : STRING;
  attribute BOX_TYPE of task_controller_if_3_wrapper : component is "black_box";
  attribute BOX_TYPE of task_controller_if_2_wrapper : component is "black_box";
  attribute BOX_TYPE of task_controller_if_1_wrapper : component is "black_box";
  attribute BOX_TYPE of task_controller_if_0_wrapper : component is "black_box";
  attribute BOX_TYPE of snoopy_if_0_wrapper : component is "black_box";
  attribute BOX_TYPE of shared_mem_if_3_wrapper : component is "black_box";
  attribute BOX_TYPE of shared_mem_if_2_wrapper : component is "black_box";
  attribute BOX_TYPE of shared_mem_if_1_wrapper : component is "black_box";
  attribute BOX_TYPE of shared_mem_if_0_wrapper : component is "black_box";
  attribute BOX_TYPE of microblaze_3_wrapper : component is "black_box";
  attribute BOX_TYPE of microblaze_2_wrapper : component is "black_box";
  attribute BOX_TYPE of microblaze_1_wrapper : component is "black_box";
  attribute BOX_TYPE of microblaze_0_wrapper : component is "black_box";
  attribute BOX_TYPE of lmb_bram_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_cntlr_3_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_cntlr_2_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_cntlr_1_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_cntlr_0_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_3_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_2_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_1_wrapper : component is "black_box";
  attribute BOX_TYPE of ilmb_0_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_cntlr_3_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_cntlr_2_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_cntlr_1_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_cntlr_0_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_3_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_2_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_1_wrapper : component is "black_box";
  attribute BOX_TYPE of dlmb_0_wrapper : component is "black_box";
  attribute BOX_TYPE of debug_module_wrapper : component is "black_box";
  attribute BOX_TYPE of dcm_0_wrapper : component is "black_box";
  attribute BOX_TYPE of bram_block_3_wrapper : component is "black_box";
  attribute BOX_TYPE of bram_block_2_wrapper : component is "black_box";
  attribute BOX_TYPE of bram_block_1_wrapper : component is "black_box";
  attribute BOX_TYPE of rs232_uart_1_wrapper : component is "black_box";
  attribute BOX_TYPE of pushbuttons_5bit_wrapper : component is "black_box";
  attribute BOX_TYPE of p3_opb_wrapper : component is "black_box";
  attribute BOX_TYPE of p2_opb_wrapper : component is "black_box";
  attribute BOX_TYPE of p1_opb_wrapper : component is "black_box";
  attribute BOX_TYPE of p0_opb_wrapper : component is "black_box";
  attribute BOX_TYPE of leds_4bit_wrapper : component is "black_box";
  attribute BOX_TYPE of dipsws_4bit_wrapper : component is "black_box";

begin

  -- Internal assignments

  fpga_0_RS232_Uart_1_RX <= fpga_0_RS232_Uart_1_RX_pin;
  fpga_0_RS232_Uart_1_TX_pin <= fpga_0_RS232_Uart_1_TX;
  dcm_clk_s <= sys_clk_pin;
  sys_rst_s <= sys_rst_pin;
  Proc0_External_Mem_Addr_pin <= shared_mem_if_0_External_Mem_Addr;
  Proc0_External_Mem_Data_Out_pin <= shared_mem_if_0_External_Mem_Data_Out;
  shared_mem_if_0_External_Mem_Data_In <= Proc0_External_Mem_Data_In_pin;
  Proc0_External_Mem_RD_WR_pin <= shared_mem_if_0_External_Mem_RD_WR;
  Proc0_External_Mem_Request_pin <= shared_mem_if_0_External_Mem_Request;
  Proc0_External_Mem_Ack_out_pin <= shared_mem_if_0_External_Mem_Ack_out;
  shared_mem_if_0_External_Mem_Ack_in <= Proc0_External_Mem_Ack_in_pin;
  Proc0_start_task_control_pin <= task_controller_if_0_start_task_control;
  Proc0_executing_pin <= task_controller_if_0_executing;
  task_controller_if_0_iteration_num <= Proc0_iteration_num_pin;
  task_controller_if_0_start_exec <= Proc0_start_exec_pin;
  task_controller_if_0_proc_done <= Proc0_proc_done_pin;
  task_controller_if_0_all_procs_done <= Proc0_all_procs_done_pin;
  task_controller_if_0_dfg_node <= Proc0_dfg_node_pin;
  Proc1_External_Mem_Addr_pin <= shared_mem_if_1_External_Mem_Addr;
  Proc1_External_Mem_Data_Out_pin <= shared_mem_if_1_External_Mem_Data_Out;
  shared_mem_if_1_External_Mem_Data_In <= Proc1_External_Mem_Data_In_pin;
  Proc1_External_Mem_RD_WR_pin <= shared_mem_if_1_External_Mem_RD_WR;
  Proc1_External_Mem_Request_pin <= shared_mem_if_1_External_Mem_Request;
  Proc1_External_Mem_Ack_out_pin <= shared_mem_if_1_External_Mem_Ack_out;
  shared_mem_if_1_External_Mem_Ack_in <= Proc1_External_Mem_Ack_in_pin;
  Proc1_executing_pin <= task_controller_if_1_executing;
  task_controller_if_1_iteration_num <= Proc1_iteration_num_pin;
  task_controller_if_1_start_exec <= Proc1_start_exec_pin;
  task_controller_if_1_dfg_node <= Proc1_dfg_node_pin;
  task_controller_if_1_proc_done <= Proc1_proc_done_pin;
  task_controller_if_1_all_procs_done <= Proc1_all_procs_done_pin;
  snoopy_proc_task_addr_pin <= snoopy_if_0_proc_task_addr;
  snoopy_info_addr_pin <= snoopy_if_0_info_addr;
  snoopy_if_0_data <= snoopy_data_pin;
  Proc2_External_Mem_Addr_pin <= shared_mem_if_2_External_Mem_Addr;
  Proc2_External_Mem_Data_Out_pin <= shared_mem_if_2_External_Mem_Data_Out;
  shared_mem_if_2_External_Mem_Data_In <= Proc2_External_Mem_Data_In_pin;
  Proc2_External_Mem_RD_WR_pin <= shared_mem_if_2_External_Mem_RD_WR;
  Proc2_External_Mem_Request_pin <= shared_mem_if_2_External_Mem_Request;
  Proc2_External_Mem_Ack_out_pin <= shared_mem_if_2_External_Mem_Ack_out;
  shared_mem_if_2_External_Mem_Ack_in <= Proc2_External_Mem_Ack_in_pin;
  Proc2_executing_pin <= task_controller_if_2_executing;
  task_controller_if_2_iteration_num <= Proc2_iteration_num_pin;
  task_controller_if_2_start_exec <= Proc2_start_exec_pin;
  task_controller_if_2_dfg_node <= Proc2_dfg_node_pin;
  task_controller_if_2_proc_done <= Proc2_proc_done_pin;
  task_controller_if_2_all_procs_done <= Proc2_all_procs_done_pin;
  Proc3_External_Mem_Addr_pin <= shared_mem_if_3_External_Mem_Addr;
  Proc3_External_Mem_Data_Out_pin <= shared_mem_if_3_External_Mem_Data_Out;
  shared_mem_if_3_External_Mem_Data_In <= Proc3_External_Mem_Data_In_pin;
  Proc3_External_Mem_RD_WR_pin <= shared_mem_if_3_External_Mem_RD_WR;
  Proc3_External_Mem_Request_pin <= shared_mem_if_3_External_Mem_Request;
  Proc3_External_Mem_Ack_out_pin <= shared_mem_if_3_External_Mem_Ack_out;
  shared_mem_if_3_External_Mem_Ack_in <= Proc3_External_Mem_Ack_in_pin;
  Proc3_executing_pin <= task_controller_if_3_executing;
  task_controller_if_3_iteration_num <= Proc3_iteration_num_pin;
  task_controller_if_3_start_exec <= Proc3_start_exec_pin;
  task_controller_if_3_dfg_node <= Proc3_dfg_node_pin;
  task_controller_if_3_proc_done <= Proc3_proc_done_pin;
  task_controller_if_3_all_procs_done <= Proc3_all_procs_done_pin;
  net_gnd0 <= '0';
  fpga_0_net_gnd_pin <= net_gnd0;
  fpga_0_net_gnd_1_pin <= net_gnd0;
  fpga_0_net_gnd_2_pin <= net_gnd0;
  fpga_0_net_gnd_3_pin <= net_gnd0;
  fpga_0_net_gnd_4_pin <= net_gnd0;
  fpga_0_net_gnd_5_pin <= net_gnd0;
  fpga_0_net_gnd_6_pin <= net_gnd0;
  net_gnd2(0 to 1) <= B"00";
  net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
  net_gnd4(0 to 3) <= B"0000";
  net_gnd5(0 to 4) <= B"00000";
  net_gnd8(0 to 7) <= B"00000000";
  net_vcc2(0 to 1) <= B"11";
  net_vcc8(0 to 7) <= B"11111111";

  task_controller_if_3 : task_controller_if_3_wrapper
    port map (
      start_task_control => open,
      executing => task_controller_if_3_executing,
      iteration_num => task_controller_if_3_iteration_num,
      start_exec => task_controller_if_3_start_exec,
      dfg_node => task_controller_if_3_dfg_node,
      proc_done => task_controller_if_3_proc_done,
      all_procs_done => task_controller_if_3_all_procs_done,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P3_opb_OPB_Rst,
      Sl_DBus => P3_opb_Sl_DBus(0 to 31),
      Sl_errAck => P3_opb_Sl_errAck(0),
      Sl_retry => P3_opb_Sl_retry(0),
      Sl_toutSup => P3_opb_Sl_toutSup(0),
      Sl_xferAck => P3_opb_Sl_xferAck(0),
      OPB_ABus => P3_opb_OPB_ABus,
      OPB_BE => P3_opb_OPB_BE,
      OPB_DBus => P3_opb_OPB_DBus,
      OPB_RNW => P3_opb_OPB_RNW,
      OPB_select => P3_opb_OPB_select,
      OPB_seqAddr => P3_opb_OPB_seqAddr
    );

  task_controller_if_2 : task_controller_if_2_wrapper
    port map (
      start_task_control => open,
      executing => task_controller_if_2_executing,
      iteration_num => task_controller_if_2_iteration_num,
      start_exec => task_controller_if_2_start_exec,
      dfg_node => task_controller_if_2_dfg_node,
      proc_done => task_controller_if_2_proc_done,
      all_procs_done => task_controller_if_2_all_procs_done,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P2_opb_OPB_Rst,
      Sl_DBus => P2_opb_Sl_DBus(0 to 31),
      Sl_errAck => P2_opb_Sl_errAck(0),
      Sl_retry => P2_opb_Sl_retry(0),
      Sl_toutSup => P2_opb_Sl_toutSup(0),
      Sl_xferAck => P2_opb_Sl_xferAck(0),
      OPB_ABus => P2_opb_OPB_ABus,
      OPB_BE => P2_opb_OPB_BE,
      OPB_DBus => P2_opb_OPB_DBus,
      OPB_RNW => P2_opb_OPB_RNW,
      OPB_select => P2_opb_OPB_select,
      OPB_seqAddr => P2_opb_OPB_seqAddr
    );

  task_controller_if_1 : task_controller_if_1_wrapper
    port map (
      start_task_control => open,
      executing => task_controller_if_1_executing,
      iteration_num => task_controller_if_1_iteration_num,
      start_exec => task_controller_if_1_start_exec,
      dfg_node => task_controller_if_1_dfg_node,
      proc_done => task_controller_if_1_proc_done,
      all_procs_done => task_controller_if_1_all_procs_done,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P1_opb_OPB_Rst,
      Sl_DBus => P1_opb_Sl_DBus(0 to 31),
      Sl_errAck => P1_opb_Sl_errAck(0),
      Sl_retry => P1_opb_Sl_retry(0),
      Sl_toutSup => P1_opb_Sl_toutSup(0),
      Sl_xferAck => P1_opb_Sl_xferAck(0),
      OPB_ABus => P1_opb_OPB_ABus,
      OPB_BE => P1_opb_OPB_BE,
      OPB_DBus => P1_opb_OPB_DBus,
      OPB_RNW => P1_opb_OPB_RNW,
      OPB_select => P1_opb_OPB_select,
      OPB_seqAddr => P1_opb_OPB_seqAddr
    );

  task_controller_if_0 : task_controller_if_0_wrapper
    port map (
      start_task_control => task_controller_if_0_start_task_control,
      executing => task_controller_if_0_executing,
      iteration_num => task_controller_if_0_iteration_num,
      start_exec => task_controller_if_0_start_exec,
      dfg_node => task_controller_if_0_dfg_node,
      proc_done => task_controller_if_0_proc_done,
      all_procs_done => task_controller_if_0_all_procs_done,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      Sl_DBus => P0_opb_Sl_DBus(0 to 31),
      Sl_errAck => P0_opb_Sl_errAck(0),
      Sl_retry => P0_opb_Sl_retry(0),
      Sl_toutSup => P0_opb_Sl_toutSup(0),
      Sl_xferAck => P0_opb_Sl_xferAck(0),
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr
    );

  snoopy_if_0 : snoopy_if_0_wrapper
    port map (
      proc_task_addr => snoopy_if_0_proc_task_addr,
      info_addr => snoopy_if_0_info_addr,
      data => snoopy_if_0_data,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      Sl_DBus => P0_opb_Sl_DBus(32 to 63),
      Sl_errAck => P0_opb_Sl_errAck(1),
      Sl_retry => P0_opb_Sl_retry(1),
      Sl_toutSup => P0_opb_Sl_toutSup(1),
      Sl_xferAck => P0_opb_Sl_xferAck(1),
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr
    );

  shared_mem_if_3 : shared_mem_if_3_wrapper
    port map (
      External_Mem_Addr => shared_mem_if_3_External_Mem_Addr,
      External_Mem_Data_Out => shared_mem_if_3_External_Mem_Data_Out,
      External_Mem_Data_In => shared_mem_if_3_External_Mem_Data_In,
      External_Mem_RD_WR => shared_mem_if_3_External_Mem_RD_WR,
      External_Mem_Request => shared_mem_if_3_External_Mem_Request,
      External_Mem_Ack_out => shared_mem_if_3_External_Mem_Ack_out,
      External_Mem_Ack_in => shared_mem_if_3_External_Mem_Ack_in,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P3_opb_OPB_Rst,
      Sl_DBus => P3_opb_Sl_DBus(32 to 63),
      Sl_errAck => P3_opb_Sl_errAck(1),
      Sl_retry => P3_opb_Sl_retry(1),
      Sl_toutSup => P3_opb_Sl_toutSup(1),
      Sl_xferAck => P3_opb_Sl_xferAck(1),
      OPB_ABus => P3_opb_OPB_ABus,
      OPB_BE => P3_opb_OPB_BE,
      OPB_DBus => P3_opb_OPB_DBus,
      OPB_RNW => P3_opb_OPB_RNW,
      OPB_select => P3_opb_OPB_select,
      OPB_seqAddr => P3_opb_OPB_seqAddr
    );

  shared_mem_if_2 : shared_mem_if_2_wrapper
    port map (
      External_Mem_Addr => shared_mem_if_2_External_Mem_Addr,
      External_Mem_Data_Out => shared_mem_if_2_External_Mem_Data_Out,
      External_Mem_Data_In => shared_mem_if_2_External_Mem_Data_In,
      External_Mem_RD_WR => shared_mem_if_2_External_Mem_RD_WR,
      External_Mem_Request => shared_mem_if_2_External_Mem_Request,
      External_Mem_Ack_out => shared_mem_if_2_External_Mem_Ack_out,
      External_Mem_Ack_in => shared_mem_if_2_External_Mem_Ack_in,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P2_opb_OPB_Rst,
      Sl_DBus => P2_opb_Sl_DBus(32 to 63),
      Sl_errAck => P2_opb_Sl_errAck(1),
      Sl_retry => P2_opb_Sl_retry(1),
      Sl_toutSup => P2_opb_Sl_toutSup(1),
      Sl_xferAck => P2_opb_Sl_xferAck(1),
      OPB_ABus => P2_opb_OPB_ABus,
      OPB_BE => P2_opb_OPB_BE,
      OPB_DBus => P2_opb_OPB_DBus,
      OPB_RNW => P2_opb_OPB_RNW,
      OPB_select => P2_opb_OPB_select,
      OPB_seqAddr => P2_opb_OPB_seqAddr
    );

  shared_mem_if_1 : shared_mem_if_1_wrapper
    port map (
      External_Mem_Addr => shared_mem_if_1_External_Mem_Addr,
      External_Mem_Data_Out => shared_mem_if_1_External_Mem_Data_Out,
      External_Mem_Data_In => shared_mem_if_1_External_Mem_Data_In,
      External_Mem_RD_WR => shared_mem_if_1_External_Mem_RD_WR,
      External_Mem_Request => shared_mem_if_1_External_Mem_Request,
      External_Mem_Ack_out => shared_mem_if_1_External_Mem_Ack_out,
      External_Mem_Ack_in => shared_mem_if_1_External_Mem_Ack_in,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P1_opb_OPB_Rst,
      Sl_DBus => P1_opb_Sl_DBus(32 to 63),
      Sl_errAck => P1_opb_Sl_errAck(1),
      Sl_retry => P1_opb_Sl_retry(1),
      Sl_toutSup => P1_opb_Sl_toutSup(1),
      Sl_xferAck => P1_opb_Sl_xferAck(1),
      OPB_ABus => P1_opb_OPB_ABus,
      OPB_BE => P1_opb_OPB_BE,
      OPB_DBus => P1_opb_OPB_DBus,
      OPB_RNW => P1_opb_OPB_RNW,
      OPB_select => P1_opb_OPB_select,
      OPB_seqAddr => P1_opb_OPB_seqAddr
    );

  shared_mem_if_0 : shared_mem_if_0_wrapper
    port map (
      External_Mem_Addr => shared_mem_if_0_External_Mem_Addr,
      External_Mem_Data_Out => shared_mem_if_0_External_Mem_Data_Out,
      External_Mem_Data_In => shared_mem_if_0_External_Mem_Data_In,
      External_Mem_RD_WR => shared_mem_if_0_External_Mem_RD_WR,
      External_Mem_Request => shared_mem_if_0_External_Mem_Request,
      External_Mem_Ack_out => shared_mem_if_0_External_Mem_Ack_out,
      External_Mem_Ack_in => shared_mem_if_0_External_Mem_Ack_in,
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      Sl_DBus => P0_opb_Sl_DBus(64 to 95),
      Sl_errAck => P0_opb_Sl_errAck(2),
      Sl_retry => P0_opb_Sl_retry(2),
      Sl_toutSup => P0_opb_Sl_toutSup(2),
      Sl_xferAck => P0_opb_Sl_xferAck(2),
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr
    );

  microblaze_3 : microblaze_3_wrapper
    port map (
      CLK => sys_clk_s,
      RESET => P3_opb_OPB_Rst,
      INTERRUPT => net_gnd0,
      DEBUG_RST => Debug_Rst,
      EXT_BRK => Ext_BRK,
      EXT_NM_BRK => Ext_NM_BRK,
      DBG_STOP => net_gnd0,
      MB_Halted => open,
      INSTR => ilmb_3_LMB_ReadDBus,
      I_ADDRTAG => open,
      IREADY => ilmb_3_LMB_Ready,
      IWAIT => net_gnd0,
      INSTR_ADDR => ilmb_3_M_ABus,
      IFETCH => ilmb_3_M_ReadStrobe,
      I_AS => ilmb_3_M_AddrStrobe,
      DATA_READ => dlmb_3_LMB_ReadDBus,
      DREADY => dlmb_3_LMB_Ready,
      DWAIT => net_gnd0,
      DATA_WRITE => dlmb_3_M_DBus,
      DATA_ADDR => dlmb_3_M_ABus,
      D_ADDRTAG => open,
      D_AS => dlmb_3_M_AddrStrobe,
      READ_STROBE => dlmb_3_M_ReadStrobe,
      WRITE_STROBE => dlmb_3_M_WriteStrobe,
      BYTE_ENABLE => dlmb_3_M_BE,
      DM_ABUS => P3_opb_M_ABus(0 to 31),
      DM_BE => P3_opb_M_BE(0 to 3),
      DM_BUSLOCK => P3_opb_M_busLock(0),
      DM_DBUS => P3_opb_M_DBus(0 to 31),
      DM_REQUEST => P3_opb_M_request(0),
      DM_RNW => P3_opb_M_RNW(0),
      DM_SELECT => P3_opb_M_select(0),
      DM_SEQADDR => P3_opb_M_seqAddr(0),
      DOPB_DBUS => P3_opb_OPB_DBus,
      DOPB_ERRACK => P3_opb_OPB_errAck,
      DOPB_MGRANT => P3_opb_OPB_MGrant(0),
      DOPB_RETRY => P3_opb_OPB_retry,
      DOPB_TIMEOUT => P3_opb_OPB_timeout,
      DOPB_XFERACK => P3_opb_OPB_xferAck,
      IM_ABUS => P3_opb_M_ABus(32 to 63),
      IM_BE => P3_opb_M_BE(4 to 7),
      IM_BUSLOCK => P3_opb_M_busLock(1),
      IM_DBUS => P3_opb_M_DBus(32 to 63),
      IM_REQUEST => P3_opb_M_request(1),
      IM_RNW => P3_opb_M_RNW(1),
      IM_SELECT => P3_opb_M_select(1),
      IM_SEQADDR => P3_opb_M_seqAddr(1),
      IOPB_DBUS => P3_opb_OPB_DBus,
      IOPB_ERRACK => P3_opb_OPB_errAck,
      IOPB_MGRANT => P3_opb_OPB_MGrant(1),
      IOPB_RETRY => P3_opb_OPB_retry,
      IOPB_TIMEOUT => P3_opb_OPB_timeout,
      IOPB_XFERACK => P3_opb_OPB_xferAck,
      DBG_CLK => net_gnd0,
      DBG_TDI => net_gnd0,
      DBG_TDO => open,
      DBG_REG_EN => net_gnd5,
      DBG_CAPTURE => net_gnd0,
      DBG_UPDATE => net_gnd0,
      Trace_Instruction => open,
      Trace_Valid_Instr => open,
      Trace_PC => open,
      Trace_Reg_Write => open,
      Trace_Reg_Addr => open,
      Trace_MSR_Reg => open,
      Trace_New_Reg_Value => open,
      Trace_Exception_Taken => open,
      Trace_Exception_Kind => open,
      Trace_Jump_Taken => open,
      Trace_Delay_Slot => open,
      Trace_Data_Address => open,
      Trace_Data_Access => open,
      Trace_Data_Read => open,
      Trace_Data_Write => open,
      Trace_Data_Write_Value => open,
      Trace_Data_Byte_Enable => open,
      Trace_DCache_Req => open,
      Trace_DCache_Hit => open,
      Trace_ICache_Req => open,
      Trace_ICache_Hit => open,
      Trace_OF_PipeRun => open,
      Trace_EX_PipeRun => open,
      Trace_MEM_PipeRun => open,
      FSL0_S_CLK => open,
      FSL0_S_READ => open,
      FSL0_S_DATA => net_gnd32,
      FSL0_S_CONTROL => net_gnd0,
      FSL0_S_EXISTS => net_gnd0,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => open,
      FSL0_M_DATA => open,
      FSL0_M_CONTROL => open,
      FSL0_M_FULL => net_gnd0,
      FSL1_S_CLK => open,
      FSL1_S_READ => open,
      FSL1_S_DATA => net_gnd32,
      FSL1_S_CONTROL => net_gnd0,
      FSL1_S_EXISTS => net_gnd0,
      FSL1_M_CLK => open,
      FSL1_M_WRITE => open,
      FSL1_M_DATA => open,
      FSL1_M_CONTROL => open,
      FSL1_M_FULL => net_gnd0,
      FSL2_S_CLK => open,
      FSL2_S_READ => open,
      FSL2_S_DATA => net_gnd32,
      FSL2_S_CONTROL => net_gnd0,
      FSL2_S_EXISTS => net_gnd0,
      FSL2_M_CLK => open,
      FSL2_M_WRITE => open,
      FSL2_M_DATA => open,
      FSL2_M_CONTROL => open,
      FSL2_M_FULL => net_gnd0,
      FSL3_S_CLK => open,
      FSL3_S_READ => open,
      FSL3_S_DATA => net_gnd32,
      FSL3_S_CONTROL => net_gnd0,
      FSL3_S_EXISTS => net_gnd0,
      FSL3_M_CLK => open,
      FSL3_M_WRITE => open,
      FSL3_M_DATA => open,
      FSL3_M_CONTROL => open,
      FSL3_M_FULL => net_gnd0,
      FSL4_S_CLK => open,
      FSL4_S_READ => open,
      FSL4_S_DATA => net_gnd32,
      FSL4_S_CONTROL => net_gnd0,
      FSL4_S_EXISTS => net_gnd0,
      FSL4_M_CLK => open,
      FSL4_M_WRITE => open,
      FSL4_M_DATA => open,
      FSL4_M_CONTROL => open,
      FSL4_M_FULL => net_gnd0,
      FSL5_S_CLK => open,
      FSL5_S_READ => open,
      FSL5_S_DATA => net_gnd32,
      FSL5_S_CONTROL => net_gnd0,
      FSL5_S_EXISTS => net_gnd0,
      FSL5_M_CLK => open,
      FSL5_M_WRITE => open,
      FSL5_M_DATA => open,
      FSL5_M_CONTROL => open,
      FSL5_M_FULL => net_gnd0,
      FSL6_S_CLK => open,
      FSL6_S_READ => open,
      FSL6_S_DATA => net_gnd32,
      FSL6_S_CONTROL => net_gnd0,
      FSL6_S_EXISTS => net_gnd0,
      FSL6_M_CLK => open,
      FSL6_M_WRITE => open,
      FSL6_M_DATA => open,
      FSL6_M_CONTROL => open,
      FSL6_M_FULL => net_gnd0,
      FSL7_S_CLK => open,
      FSL7_S_READ => open,
      FSL7_S_DATA => net_gnd32,
      FSL7_S_CONTROL => net_gnd0,
      FSL7_S_EXISTS => net_gnd0,
      FSL7_M_CLK => open,
      FSL7_M_WRITE => open,
      FSL7_M_DATA => open,
      FSL7_M_CONTROL => open,
      FSL7_M_FULL => net_gnd0,
      ICACHE_FSL_IN_CLK => open,
      ICACHE_FSL_IN_READ => open,
      ICACHE_FSL_IN_DATA => net_gnd32,
      ICACHE_FSL_IN_CONTROL => net_gnd0,
      ICACHE_FSL_IN_EXISTS => net_gnd0,
      ICACHE_FSL_OUT_CLK => open,
      ICACHE_FSL_OUT_WRITE => open,
      ICACHE_FSL_OUT_DATA => open,
      ICACHE_FSL_OUT_CONTROL => open,
      ICACHE_FSL_OUT_FULL => net_gnd0,
      DCACHE_FSL_IN_CLK => open,
      DCACHE_FSL_IN_READ => open,
      DCACHE_FSL_IN_DATA => net_gnd32,
      DCACHE_FSL_IN_CONTROL => net_gnd0,
      DCACHE_FSL_IN_EXISTS => net_gnd0,
      DCACHE_FSL_OUT_CLK => open,
      DCACHE_FSL_OUT_WRITE => open,
      DCACHE_FSL_OUT_DATA => open,
      DCACHE_FSL_OUT_CONTROL => open,
      DCACHE_FSL_OUT_FULL => net_gnd0
    );

  microblaze_2 : microblaze_2_wrapper
    port map (
      CLK => sys_clk_s,
      RESET => P2_opb_OPB_Rst,
      INTERRUPT => net_gnd0,
      DEBUG_RST => Debug_Rst,
      EXT_BRK => Ext_BRK,
      EXT_NM_BRK => Ext_NM_BRK,
      DBG_STOP => net_gnd0,
      MB_Halted => open,
      INSTR => ilmb_2_LMB_ReadDBus,
      I_ADDRTAG => open,
      IREADY => ilmb_2_LMB_Ready,
      IWAIT => net_gnd0,
      INSTR_ADDR => ilmb_2_M_ABus,
      IFETCH => ilmb_2_M_ReadStrobe,
      I_AS => ilmb_2_M_AddrStrobe,
      DATA_READ => dlmb_2_LMB_ReadDBus,
      DREADY => dlmb_2_LMB_Ready,
      DWAIT => net_gnd0,
      DATA_WRITE => dlmb_2_M_DBus,
      DATA_ADDR => dlmb_2_M_ABus,
      D_ADDRTAG => open,
      D_AS => dlmb_2_M_AddrStrobe,
      READ_STROBE => dlmb_2_M_ReadStrobe,
      WRITE_STROBE => dlmb_2_M_WriteStrobe,
      BYTE_ENABLE => dlmb_2_M_BE,
      DM_ABUS => P2_opb_M_ABus(0 to 31),
      DM_BE => P2_opb_M_BE(0 to 3),
      DM_BUSLOCK => P2_opb_M_busLock(0),
      DM_DBUS => P2_opb_M_DBus(0 to 31),
      DM_REQUEST => P2_opb_M_request(0),
      DM_RNW => P2_opb_M_RNW(0),
      DM_SELECT => P2_opb_M_select(0),
      DM_SEQADDR => P2_opb_M_seqAddr(0),
      DOPB_DBUS => P2_opb_OPB_DBus,
      DOPB_ERRACK => P2_opb_OPB_errAck,
      DOPB_MGRANT => P2_opb_OPB_MGrant(0),
      DOPB_RETRY => P2_opb_OPB_retry,
      DOPB_TIMEOUT => P2_opb_OPB_timeout,
      DOPB_XFERACK => P2_opb_OPB_xferAck,
      IM_ABUS => P2_opb_M_ABus(32 to 63),
      IM_BE => P2_opb_M_BE(4 to 7),
      IM_BUSLOCK => P2_opb_M_busLock(1),
      IM_DBUS => P2_opb_M_DBus(32 to 63),
      IM_REQUEST => P2_opb_M_request(1),
      IM_RNW => P2_opb_M_RNW(1),
      IM_SELECT => P2_opb_M_select(1),
      IM_SEQADDR => P2_opb_M_seqAddr(1),
      IOPB_DBUS => P2_opb_OPB_DBus,
      IOPB_ERRACK => P2_opb_OPB_errAck,
      IOPB_MGRANT => P2_opb_OPB_MGrant(1),
      IOPB_RETRY => P2_opb_OPB_retry,
      IOPB_TIMEOUT => P2_opb_OPB_timeout,
      IOPB_XFERACK => P2_opb_OPB_xferAck,
      DBG_CLK => net_gnd0,
      DBG_TDI => net_gnd0,
      DBG_TDO => open,
      DBG_REG_EN => net_gnd5,
      DBG_CAPTURE => net_gnd0,
      DBG_UPDATE => net_gnd0,
      Trace_Instruction => open,
      Trace_Valid_Instr => open,
      Trace_PC => open,
      Trace_Reg_Write => open,
      Trace_Reg_Addr => open,
      Trace_MSR_Reg => open,
      Trace_New_Reg_Value => open,
      Trace_Exception_Taken => open,
      Trace_Exception_Kind => open,
      Trace_Jump_Taken => open,
      Trace_Delay_Slot => open,
      Trace_Data_Address => open,
      Trace_Data_Access => open,
      Trace_Data_Read => open,
      Trace_Data_Write => open,
      Trace_Data_Write_Value => open,
      Trace_Data_Byte_Enable => open,
      Trace_DCache_Req => open,
      Trace_DCache_Hit => open,
      Trace_ICache_Req => open,
      Trace_ICache_Hit => open,
      Trace_OF_PipeRun => open,
      Trace_EX_PipeRun => open,
      Trace_MEM_PipeRun => open,
      FSL0_S_CLK => open,
      FSL0_S_READ => open,
      FSL0_S_DATA => net_gnd32,
      FSL0_S_CONTROL => net_gnd0,
      FSL0_S_EXISTS => net_gnd0,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => open,
      FSL0_M_DATA => open,
      FSL0_M_CONTROL => open,
      FSL0_M_FULL => net_gnd0,
      FSL1_S_CLK => open,
      FSL1_S_READ => open,
      FSL1_S_DATA => net_gnd32,
      FSL1_S_CONTROL => net_gnd0,
      FSL1_S_EXISTS => net_gnd0,
      FSL1_M_CLK => open,
      FSL1_M_WRITE => open,
      FSL1_M_DATA => open,
      FSL1_M_CONTROL => open,
      FSL1_M_FULL => net_gnd0,
      FSL2_S_CLK => open,
      FSL2_S_READ => open,
      FSL2_S_DATA => net_gnd32,
      FSL2_S_CONTROL => net_gnd0,
      FSL2_S_EXISTS => net_gnd0,
      FSL2_M_CLK => open,
      FSL2_M_WRITE => open,
      FSL2_M_DATA => open,
      FSL2_M_CONTROL => open,
      FSL2_M_FULL => net_gnd0,
      FSL3_S_CLK => open,
      FSL3_S_READ => open,
      FSL3_S_DATA => net_gnd32,
      FSL3_S_CONTROL => net_gnd0,
      FSL3_S_EXISTS => net_gnd0,
      FSL3_M_CLK => open,
      FSL3_M_WRITE => open,
      FSL3_M_DATA => open,
      FSL3_M_CONTROL => open,
      FSL3_M_FULL => net_gnd0,
      FSL4_S_CLK => open,
      FSL4_S_READ => open,
      FSL4_S_DATA => net_gnd32,
      FSL4_S_CONTROL => net_gnd0,
      FSL4_S_EXISTS => net_gnd0,
      FSL4_M_CLK => open,
      FSL4_M_WRITE => open,
      FSL4_M_DATA => open,
      FSL4_M_CONTROL => open,
      FSL4_M_FULL => net_gnd0,
      FSL5_S_CLK => open,
      FSL5_S_READ => open,
      FSL5_S_DATA => net_gnd32,
      FSL5_S_CONTROL => net_gnd0,
      FSL5_S_EXISTS => net_gnd0,
      FSL5_M_CLK => open,
      FSL5_M_WRITE => open,
      FSL5_M_DATA => open,
      FSL5_M_CONTROL => open,
      FSL5_M_FULL => net_gnd0,
      FSL6_S_CLK => open,
      FSL6_S_READ => open,
      FSL6_S_DATA => net_gnd32,
      FSL6_S_CONTROL => net_gnd0,
      FSL6_S_EXISTS => net_gnd0,
      FSL6_M_CLK => open,
      FSL6_M_WRITE => open,
      FSL6_M_DATA => open,
      FSL6_M_CONTROL => open,
      FSL6_M_FULL => net_gnd0,
      FSL7_S_CLK => open,
      FSL7_S_READ => open,
      FSL7_S_DATA => net_gnd32,
      FSL7_S_CONTROL => net_gnd0,
      FSL7_S_EXISTS => net_gnd0,
      FSL7_M_CLK => open,
      FSL7_M_WRITE => open,
      FSL7_M_DATA => open,
      FSL7_M_CONTROL => open,
      FSL7_M_FULL => net_gnd0,
      ICACHE_FSL_IN_CLK => open,
      ICACHE_FSL_IN_READ => open,
      ICACHE_FSL_IN_DATA => net_gnd32,
      ICACHE_FSL_IN_CONTROL => net_gnd0,
      ICACHE_FSL_IN_EXISTS => net_gnd0,
      ICACHE_FSL_OUT_CLK => open,
      ICACHE_FSL_OUT_WRITE => open,
      ICACHE_FSL_OUT_DATA => open,
      ICACHE_FSL_OUT_CONTROL => open,
      ICACHE_FSL_OUT_FULL => net_gnd0,
      DCACHE_FSL_IN_CLK => open,
      DCACHE_FSL_IN_READ => open,
      DCACHE_FSL_IN_DATA => net_gnd32,
      DCACHE_FSL_IN_CONTROL => net_gnd0,
      DCACHE_FSL_IN_EXISTS => net_gnd0,
      DCACHE_FSL_OUT_CLK => open,
      DCACHE_FSL_OUT_WRITE => open,
      DCACHE_FSL_OUT_DATA => open,
      DCACHE_FSL_OUT_CONTROL => open,
      DCACHE_FSL_OUT_FULL => net_gnd0
    );

  microblaze_1 : microblaze_1_wrapper
    port map (
      CLK => sys_clk_s,
      RESET => P1_opb_OPB_Rst,
      INTERRUPT => net_gnd0,
      DEBUG_RST => Debug_Rst,
      EXT_BRK => Ext_BRK,
      EXT_NM_BRK => Ext_NM_BRK,
      DBG_STOP => net_gnd0,
      MB_Halted => open,
      INSTR => ilmb_1_LMB_ReadDBus,
      I_ADDRTAG => open,
      IREADY => ilmb_1_LMB_Ready,
      IWAIT => net_gnd0,
      INSTR_ADDR => ilmb_1_M_ABus,
      IFETCH => ilmb_1_M_ReadStrobe,
      I_AS => ilmb_1_M_AddrStrobe,
      DATA_READ => dlmb_1_LMB_ReadDBus,
      DREADY => dlmb_1_LMB_Ready,
      DWAIT => net_gnd0,
      DATA_WRITE => dlmb_1_M_DBus,
      DATA_ADDR => dlmb_1_M_ABus,
      D_ADDRTAG => open,
      D_AS => dlmb_1_M_AddrStrobe,
      READ_STROBE => dlmb_1_M_ReadStrobe,
      WRITE_STROBE => dlmb_1_M_WriteStrobe,
      BYTE_ENABLE => dlmb_1_M_BE,
      DM_ABUS => P1_opb_M_ABus(0 to 31),
      DM_BE => P1_opb_M_BE(0 to 3),
      DM_BUSLOCK => P1_opb_M_busLock(0),
      DM_DBUS => P1_opb_M_DBus(0 to 31),
      DM_REQUEST => P1_opb_M_request(0),
      DM_RNW => P1_opb_M_RNW(0),
      DM_SELECT => P1_opb_M_select(0),
      DM_SEQADDR => P1_opb_M_seqAddr(0),
      DOPB_DBUS => P1_opb_OPB_DBus,
      DOPB_ERRACK => P1_opb_OPB_errAck,
      DOPB_MGRANT => P1_opb_OPB_MGrant(0),
      DOPB_RETRY => P1_opb_OPB_retry,
      DOPB_TIMEOUT => P1_opb_OPB_timeout,
      DOPB_XFERACK => P1_opb_OPB_xferAck,
      IM_ABUS => P1_opb_M_ABus(32 to 63),
      IM_BE => P1_opb_M_BE(4 to 7),
      IM_BUSLOCK => P1_opb_M_busLock(1),
      IM_DBUS => P1_opb_M_DBus(32 to 63),
      IM_REQUEST => P1_opb_M_request(1),
      IM_RNW => P1_opb_M_RNW(1),
      IM_SELECT => P1_opb_M_select(1),
      IM_SEQADDR => P1_opb_M_seqAddr(1),
      IOPB_DBUS => P1_opb_OPB_DBus,
      IOPB_ERRACK => P1_opb_OPB_errAck,
      IOPB_MGRANT => P1_opb_OPB_MGrant(1),
      IOPB_RETRY => P1_opb_OPB_retry,
      IOPB_TIMEOUT => P1_opb_OPB_timeout,
      IOPB_XFERACK => P1_opb_OPB_xferAck,
      DBG_CLK => net_gnd0,
      DBG_TDI => net_gnd0,
      DBG_TDO => open,
      DBG_REG_EN => net_gnd5,
      DBG_CAPTURE => net_gnd0,
      DBG_UPDATE => net_gnd0,
      Trace_Instruction => open,
      Trace_Valid_Instr => open,
      Trace_PC => open,
      Trace_Reg_Write => open,
      Trace_Reg_Addr => open,
      Trace_MSR_Reg => open,
      Trace_New_Reg_Value => open,
      Trace_Exception_Taken => open,
      Trace_Exception_Kind => open,
      Trace_Jump_Taken => open,
      Trace_Delay_Slot => open,
      Trace_Data_Address => open,
      Trace_Data_Access => open,
      Trace_Data_Read => open,
      Trace_Data_Write => open,
      Trace_Data_Write_Value => open,
      Trace_Data_Byte_Enable => open,
      Trace_DCache_Req => open,
      Trace_DCache_Hit => open,
      Trace_ICache_Req => open,
      Trace_ICache_Hit => open,
      Trace_OF_PipeRun => open,
      Trace_EX_PipeRun => open,
      Trace_MEM_PipeRun => open,
      FSL0_S_CLK => open,
      FSL0_S_READ => open,
      FSL0_S_DATA => net_gnd32,
      FSL0_S_CONTROL => net_gnd0,
      FSL0_S_EXISTS => net_gnd0,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => open,
      FSL0_M_DATA => open,
      FSL0_M_CONTROL => open,
      FSL0_M_FULL => net_gnd0,
      FSL1_S_CLK => open,
      FSL1_S_READ => open,
      FSL1_S_DATA => net_gnd32,
      FSL1_S_CONTROL => net_gnd0,
      FSL1_S_EXISTS => net_gnd0,
      FSL1_M_CLK => open,
      FSL1_M_WRITE => open,
      FSL1_M_DATA => open,
      FSL1_M_CONTROL => open,
      FSL1_M_FULL => net_gnd0,
      FSL2_S_CLK => open,
      FSL2_S_READ => open,
      FSL2_S_DATA => net_gnd32,
      FSL2_S_CONTROL => net_gnd0,
      FSL2_S_EXISTS => net_gnd0,
      FSL2_M_CLK => open,
      FSL2_M_WRITE => open,
      FSL2_M_DATA => open,
      FSL2_M_CONTROL => open,
      FSL2_M_FULL => net_gnd0,
      FSL3_S_CLK => open,
      FSL3_S_READ => open,
      FSL3_S_DATA => net_gnd32,
      FSL3_S_CONTROL => net_gnd0,
      FSL3_S_EXISTS => net_gnd0,
      FSL3_M_CLK => open,
      FSL3_M_WRITE => open,
      FSL3_M_DATA => open,
      FSL3_M_CONTROL => open,
      FSL3_M_FULL => net_gnd0,
      FSL4_S_CLK => open,
      FSL4_S_READ => open,
      FSL4_S_DATA => net_gnd32,
      FSL4_S_CONTROL => net_gnd0,
      FSL4_S_EXISTS => net_gnd0,
      FSL4_M_CLK => open,
      FSL4_M_WRITE => open,
      FSL4_M_DATA => open,
      FSL4_M_CONTROL => open,
      FSL4_M_FULL => net_gnd0,
      FSL5_S_CLK => open,
      FSL5_S_READ => open,
      FSL5_S_DATA => net_gnd32,
      FSL5_S_CONTROL => net_gnd0,
      FSL5_S_EXISTS => net_gnd0,
      FSL5_M_CLK => open,
      FSL5_M_WRITE => open,
      FSL5_M_DATA => open,
      FSL5_M_CONTROL => open,
      FSL5_M_FULL => net_gnd0,
      FSL6_S_CLK => open,
      FSL6_S_READ => open,
      FSL6_S_DATA => net_gnd32,
      FSL6_S_CONTROL => net_gnd0,
      FSL6_S_EXISTS => net_gnd0,
      FSL6_M_CLK => open,
      FSL6_M_WRITE => open,
      FSL6_M_DATA => open,
      FSL6_M_CONTROL => open,
      FSL6_M_FULL => net_gnd0,
      FSL7_S_CLK => open,
      FSL7_S_READ => open,
      FSL7_S_DATA => net_gnd32,
      FSL7_S_CONTROL => net_gnd0,
      FSL7_S_EXISTS => net_gnd0,
      FSL7_M_CLK => open,
      FSL7_M_WRITE => open,
      FSL7_M_DATA => open,
      FSL7_M_CONTROL => open,
      FSL7_M_FULL => net_gnd0,
      ICACHE_FSL_IN_CLK => open,
      ICACHE_FSL_IN_READ => open,
      ICACHE_FSL_IN_DATA => net_gnd32,
      ICACHE_FSL_IN_CONTROL => net_gnd0,
      ICACHE_FSL_IN_EXISTS => net_gnd0,
      ICACHE_FSL_OUT_CLK => open,
      ICACHE_FSL_OUT_WRITE => open,
      ICACHE_FSL_OUT_DATA => open,
      ICACHE_FSL_OUT_CONTROL => open,
      ICACHE_FSL_OUT_FULL => net_gnd0,
      DCACHE_FSL_IN_CLK => open,
      DCACHE_FSL_IN_READ => open,
      DCACHE_FSL_IN_DATA => net_gnd32,
      DCACHE_FSL_IN_CONTROL => net_gnd0,
      DCACHE_FSL_IN_EXISTS => net_gnd0,
      DCACHE_FSL_OUT_CLK => open,
      DCACHE_FSL_OUT_WRITE => open,
      DCACHE_FSL_OUT_DATA => open,
      DCACHE_FSL_OUT_CONTROL => open,
      DCACHE_FSL_OUT_FULL => net_gnd0
    );

  microblaze_0 : microblaze_0_wrapper
    port map (
      CLK => sys_clk_s,
      RESET => P0_opb_OPB_Rst,
      INTERRUPT => net_gnd0,
      DEBUG_RST => Debug_Rst,
      EXT_BRK => Ext_BRK,
      EXT_NM_BRK => Ext_NM_BRK,
      DBG_STOP => net_gnd0,
      MB_Halted => open,
      INSTR => ilmb_0_LMB_ReadDBus,
      I_ADDRTAG => open,
      IREADY => ilmb_0_LMB_Ready,
      IWAIT => net_gnd0,
      INSTR_ADDR => ilmb_0_M_ABus,
      IFETCH => ilmb_0_M_ReadStrobe,
      I_AS => ilmb_0_M_AddrStrobe,
      DATA_READ => dlmb_0_LMB_ReadDBus,
      DREADY => dlmb_0_LMB_Ready,
      DWAIT => net_gnd0,
      DATA_WRITE => dlmb_0_M_DBus,
      DATA_ADDR => dlmb_0_M_ABus,
      D_ADDRTAG => open,
      D_AS => dlmb_0_M_AddrStrobe,
      READ_STROBE => dlmb_0_M_ReadStrobe,
      WRITE_STROBE => dlmb_0_M_WriteStrobe,
      BYTE_ENABLE => dlmb_0_M_BE,
      DM_ABUS => P0_opb_M_ABus(0 to 31),
      DM_BE => P0_opb_M_BE(0 to 3),
      DM_BUSLOCK => P0_opb_M_busLock(0),
      DM_DBUS => P0_opb_M_DBus(0 to 31),
      DM_REQUEST => P0_opb_M_request(0),
      DM_RNW => P0_opb_M_RNW(0),
      DM_SELECT => P0_opb_M_select(0),
      DM_SEQADDR => P0_opb_M_seqAddr(0),
      DOPB_DBUS => P0_opb_OPB_DBus,
      DOPB_ERRACK => P0_opb_OPB_errAck,
      DOPB_MGRANT => P0_opb_OPB_MGrant(0),
      DOPB_RETRY => P0_opb_OPB_retry,
      DOPB_TIMEOUT => P0_opb_OPB_timeout,
      DOPB_XFERACK => P0_opb_OPB_xferAck,
      IM_ABUS => P0_opb_M_ABus(32 to 63),
      IM_BE => P0_opb_M_BE(4 to 7),
      IM_BUSLOCK => P0_opb_M_busLock(1),
      IM_DBUS => P0_opb_M_DBus(32 to 63),
      IM_REQUEST => P0_opb_M_request(1),
      IM_RNW => P0_opb_M_RNW(1),
      IM_SELECT => P0_opb_M_select(1),
      IM_SEQADDR => P0_opb_M_seqAddr(1),
      IOPB_DBUS => P0_opb_OPB_DBus,
      IOPB_ERRACK => P0_opb_OPB_errAck,
      IOPB_MGRANT => P0_opb_OPB_MGrant(1),
      IOPB_RETRY => P0_opb_OPB_retry,
      IOPB_TIMEOUT => P0_opb_OPB_timeout,
      IOPB_XFERACK => P0_opb_OPB_xferAck,
      DBG_CLK => DBG_CLK_s,
      DBG_TDI => DBG_TDI_s,
      DBG_TDO => DBG_TDO_s,
      DBG_REG_EN => DBG_REG_EN_s,
      DBG_CAPTURE => DBG_CAPTURE_s,
      DBG_UPDATE => DBG_UPDATE_s,
      Trace_Instruction => open,
      Trace_Valid_Instr => open,
      Trace_PC => open,
      Trace_Reg_Write => open,
      Trace_Reg_Addr => open,
      Trace_MSR_Reg => open,
      Trace_New_Reg_Value => open,
      Trace_Exception_Taken => open,
      Trace_Exception_Kind => open,
      Trace_Jump_Taken => open,
      Trace_Delay_Slot => open,
      Trace_Data_Address => open,
      Trace_Data_Access => open,
      Trace_Data_Read => open,
      Trace_Data_Write => open,
      Trace_Data_Write_Value => open,
      Trace_Data_Byte_Enable => open,
      Trace_DCache_Req => open,
      Trace_DCache_Hit => open,
      Trace_ICache_Req => open,
      Trace_ICache_Hit => open,
      Trace_OF_PipeRun => open,
      Trace_EX_PipeRun => open,
      Trace_MEM_PipeRun => open,
      FSL0_S_CLK => open,
      FSL0_S_READ => open,
      FSL0_S_DATA => net_gnd32,
      FSL0_S_CONTROL => net_gnd0,
      FSL0_S_EXISTS => net_gnd0,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => open,
      FSL0_M_DATA => open,
      FSL0_M_CONTROL => open,
      FSL0_M_FULL => net_gnd0,
      FSL1_S_CLK => open,
      FSL1_S_READ => open,
      FSL1_S_DATA => net_gnd32,
      FSL1_S_CONTROL => net_gnd0,
      FSL1_S_EXISTS => net_gnd0,
      FSL1_M_CLK => open,
      FSL1_M_WRITE => open,
      FSL1_M_DATA => open,
      FSL1_M_CONTROL => open,
      FSL1_M_FULL => net_gnd0,
      FSL2_S_CLK => open,
      FSL2_S_READ => open,
      FSL2_S_DATA => net_gnd32,
      FSL2_S_CONTROL => net_gnd0,
      FSL2_S_EXISTS => net_gnd0,
      FSL2_M_CLK => open,
      FSL2_M_WRITE => open,
      FSL2_M_DATA => open,
      FSL2_M_CONTROL => open,
      FSL2_M_FULL => net_gnd0,
      FSL3_S_CLK => open,
      FSL3_S_READ => open,
      FSL3_S_DATA => net_gnd32,
      FSL3_S_CONTROL => net_gnd0,
      FSL3_S_EXISTS => net_gnd0,
      FSL3_M_CLK => open,
      FSL3_M_WRITE => open,
      FSL3_M_DATA => open,
      FSL3_M_CONTROL => open,
      FSL3_M_FULL => net_gnd0,
      FSL4_S_CLK => open,
      FSL4_S_READ => open,
      FSL4_S_DATA => net_gnd32,
      FSL4_S_CONTROL => net_gnd0,
      FSL4_S_EXISTS => net_gnd0,
      FSL4_M_CLK => open,
      FSL4_M_WRITE => open,
      FSL4_M_DATA => open,
      FSL4_M_CONTROL => open,
      FSL4_M_FULL => net_gnd0,
      FSL5_S_CLK => open,
      FSL5_S_READ => open,
      FSL5_S_DATA => net_gnd32,
      FSL5_S_CONTROL => net_gnd0,
      FSL5_S_EXISTS => net_gnd0,
      FSL5_M_CLK => open,
      FSL5_M_WRITE => open,
      FSL5_M_DATA => open,
      FSL5_M_CONTROL => open,
      FSL5_M_FULL => net_gnd0,
      FSL6_S_CLK => open,
      FSL6_S_READ => open,
      FSL6_S_DATA => net_gnd32,
      FSL6_S_CONTROL => net_gnd0,
      FSL6_S_EXISTS => net_gnd0,
      FSL6_M_CLK => open,
      FSL6_M_WRITE => open,
      FSL6_M_DATA => open,
      FSL6_M_CONTROL => open,
      FSL6_M_FULL => net_gnd0,
      FSL7_S_CLK => open,
      FSL7_S_READ => open,
      FSL7_S_DATA => net_gnd32,
      FSL7_S_CONTROL => net_gnd0,
      FSL7_S_EXISTS => net_gnd0,
      FSL7_M_CLK => open,
      FSL7_M_WRITE => open,
      FSL7_M_DATA => open,
      FSL7_M_CONTROL => open,
      FSL7_M_FULL => net_gnd0,
      ICACHE_FSL_IN_CLK => open,
      ICACHE_FSL_IN_READ => open,
      ICACHE_FSL_IN_DATA => net_gnd32,
      ICACHE_FSL_IN_CONTROL => net_gnd0,
      ICACHE_FSL_IN_EXISTS => net_gnd0,
      ICACHE_FSL_OUT_CLK => open,
      ICACHE_FSL_OUT_WRITE => open,
      ICACHE_FSL_OUT_DATA => open,
      ICACHE_FSL_OUT_CONTROL => open,
      ICACHE_FSL_OUT_FULL => net_gnd0,
      DCACHE_FSL_IN_CLK => open,
      DCACHE_FSL_IN_READ => open,
      DCACHE_FSL_IN_DATA => net_gnd32,
      DCACHE_FSL_IN_CONTROL => net_gnd0,
      DCACHE_FSL_IN_EXISTS => net_gnd0,
      DCACHE_FSL_OUT_CLK => open,
      DCACHE_FSL_OUT_WRITE => open,
      DCACHE_FSL_OUT_DATA => open,
      DCACHE_FSL_OUT_CONTROL => open,
      DCACHE_FSL_OUT_FULL => net_gnd0
    );

  lmb_bram : lmb_bram_wrapper
    port map (
      BRAM_Rst_A => ilmb_port_BRAM_Rst,
      BRAM_Clk_A => ilmb_port_BRAM_Clk,
      BRAM_EN_A => ilmb_port_BRAM_EN,
      BRAM_WEN_A => ilmb_port_BRAM_WEN,
      BRAM_Addr_A => ilmb_port_BRAM_Addr,
      BRAM_Din_A => ilmb_port_BRAM_Din,
      BRAM_Dout_A => ilmb_port_BRAM_Dout,
      BRAM_Rst_B => dlmb_port_BRAM_Rst,
      BRAM_Clk_B => dlmb_port_BRAM_Clk,
      BRAM_EN_B => dlmb_port_BRAM_EN,
      BRAM_WEN_B => dlmb_port_BRAM_WEN,
      BRAM_Addr_B => dlmb_port_BRAM_Addr,
      BRAM_Din_B => dlmb_port_BRAM_Din,
      BRAM_Dout_B => dlmb_port_BRAM_Dout
    );

  ilmb_cntlr_3 : ilmb_cntlr_3_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => ilmb_3_OPB_Rst,
      LMB_ABus => ilmb_3_LMB_ABus,
      LMB_WriteDBus => ilmb_3_LMB_WriteDBus,
      LMB_AddrStrobe => ilmb_3_LMB_AddrStrobe,
      LMB_ReadStrobe => ilmb_3_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_3_LMB_WriteStrobe,
      LMB_BE => ilmb_3_LMB_BE,
      Sl_DBus => ilmb_3_Sl_DBus,
      Sl_Ready => ilmb_3_Sl_Ready(0),
      BRAM_Rst_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_3_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_3_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Dout
    );

  ilmb_cntlr_2 : ilmb_cntlr_2_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => ilmb_2_OPB_Rst,
      LMB_ABus => ilmb_2_LMB_ABus,
      LMB_WriteDBus => ilmb_2_LMB_WriteDBus,
      LMB_AddrStrobe => ilmb_2_LMB_AddrStrobe,
      LMB_ReadStrobe => ilmb_2_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_2_LMB_WriteStrobe,
      LMB_BE => ilmb_2_LMB_BE,
      Sl_DBus => ilmb_2_Sl_DBus,
      Sl_Ready => ilmb_2_Sl_Ready(0),
      BRAM_Rst_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_2_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_2_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Dout
    );

  ilmb_cntlr_1 : ilmb_cntlr_1_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => ilmb_1_OPB_Rst,
      LMB_ABus => ilmb_1_LMB_ABus,
      LMB_WriteDBus => ilmb_1_LMB_WriteDBus,
      LMB_AddrStrobe => ilmb_1_LMB_AddrStrobe,
      LMB_ReadStrobe => ilmb_1_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_1_LMB_WriteStrobe,
      LMB_BE => ilmb_1_LMB_BE,
      Sl_DBus => ilmb_1_Sl_DBus,
      Sl_Ready => ilmb_1_Sl_Ready(0),
      BRAM_Rst_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_1_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_1_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Dout
    );

  ilmb_cntlr_0 : ilmb_cntlr_0_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => ilmb_0_OPB_Rst,
      LMB_ABus => ilmb_0_LMB_ABus,
      LMB_WriteDBus => ilmb_0_LMB_WriteDBus,
      LMB_AddrStrobe => ilmb_0_LMB_AddrStrobe,
      LMB_ReadStrobe => ilmb_0_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_0_LMB_WriteStrobe,
      LMB_BE => ilmb_0_LMB_BE,
      Sl_DBus => ilmb_0_Sl_DBus,
      Sl_Ready => ilmb_0_Sl_Ready(0),
      BRAM_Rst_A => ilmb_port_BRAM_Rst,
      BRAM_Clk_A => ilmb_port_BRAM_Clk,
      BRAM_EN_A => ilmb_port_BRAM_EN,
      BRAM_WEN_A => ilmb_port_BRAM_WEN,
      BRAM_Addr_A => ilmb_port_BRAM_Addr,
      BRAM_Din_A => ilmb_port_BRAM_Din,
      BRAM_Dout_A => ilmb_port_BRAM_Dout
    );

  ilmb_3 : ilmb_3_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => ilmb_3_OPB_Rst,
      M_ABus => ilmb_3_M_ABus,
      M_ReadStrobe => ilmb_3_M_ReadStrobe,
      M_WriteStrobe => net_gnd0,
      M_AddrStrobe => ilmb_3_M_AddrStrobe,
      M_DBus => net_gnd32,
      M_BE => net_gnd4,
      Sl_DBus => ilmb_3_Sl_DBus,
      Sl_Ready => ilmb_3_Sl_Ready(0 to 0),
      LMB_ABus => ilmb_3_LMB_ABus,
      LMB_ReadStrobe => ilmb_3_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_3_LMB_WriteStrobe,
      LMB_AddrStrobe => ilmb_3_LMB_AddrStrobe,
      LMB_ReadDBus => ilmb_3_LMB_ReadDBus,
      LMB_WriteDBus => ilmb_3_LMB_WriteDBus,
      LMB_Ready => ilmb_3_LMB_Ready,
      LMB_BE => ilmb_3_LMB_BE
    );

  ilmb_2 : ilmb_2_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => ilmb_2_OPB_Rst,
      M_ABus => ilmb_2_M_ABus,
      M_ReadStrobe => ilmb_2_M_ReadStrobe,
      M_WriteStrobe => net_gnd0,
      M_AddrStrobe => ilmb_2_M_AddrStrobe,
      M_DBus => net_gnd32,
      M_BE => net_gnd4,
      Sl_DBus => ilmb_2_Sl_DBus,
      Sl_Ready => ilmb_2_Sl_Ready(0 to 0),
      LMB_ABus => ilmb_2_LMB_ABus,
      LMB_ReadStrobe => ilmb_2_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_2_LMB_WriteStrobe,
      LMB_AddrStrobe => ilmb_2_LMB_AddrStrobe,
      LMB_ReadDBus => ilmb_2_LMB_ReadDBus,
      LMB_WriteDBus => ilmb_2_LMB_WriteDBus,
      LMB_Ready => ilmb_2_LMB_Ready,
      LMB_BE => ilmb_2_LMB_BE
    );

  ilmb_1 : ilmb_1_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => ilmb_1_OPB_Rst,
      M_ABus => ilmb_1_M_ABus,
      M_ReadStrobe => ilmb_1_M_ReadStrobe,
      M_WriteStrobe => net_gnd0,
      M_AddrStrobe => ilmb_1_M_AddrStrobe,
      M_DBus => net_gnd32,
      M_BE => net_gnd4,
      Sl_DBus => ilmb_1_Sl_DBus,
      Sl_Ready => ilmb_1_Sl_Ready(0 to 0),
      LMB_ABus => ilmb_1_LMB_ABus,
      LMB_ReadStrobe => ilmb_1_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_1_LMB_WriteStrobe,
      LMB_AddrStrobe => ilmb_1_LMB_AddrStrobe,
      LMB_ReadDBus => ilmb_1_LMB_ReadDBus,
      LMB_WriteDBus => ilmb_1_LMB_WriteDBus,
      LMB_Ready => ilmb_1_LMB_Ready,
      LMB_BE => ilmb_1_LMB_BE
    );

  ilmb_0 : ilmb_0_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => ilmb_0_OPB_Rst,
      M_ABus => ilmb_0_M_ABus,
      M_ReadStrobe => ilmb_0_M_ReadStrobe,
      M_WriteStrobe => net_gnd0,
      M_AddrStrobe => ilmb_0_M_AddrStrobe,
      M_DBus => net_gnd32,
      M_BE => net_gnd4,
      Sl_DBus => ilmb_0_Sl_DBus,
      Sl_Ready => ilmb_0_Sl_Ready(0 to 0),
      LMB_ABus => ilmb_0_LMB_ABus,
      LMB_ReadStrobe => ilmb_0_LMB_ReadStrobe,
      LMB_WriteStrobe => ilmb_0_LMB_WriteStrobe,
      LMB_AddrStrobe => ilmb_0_LMB_AddrStrobe,
      LMB_ReadDBus => ilmb_0_LMB_ReadDBus,
      LMB_WriteDBus => ilmb_0_LMB_WriteDBus,
      LMB_Ready => ilmb_0_LMB_Ready,
      LMB_BE => ilmb_0_LMB_BE
    );

  dlmb_cntlr_3 : dlmb_cntlr_3_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => dlmb_3_OPB_Rst,
      LMB_ABus => dlmb_3_LMB_ABus,
      LMB_WriteDBus => dlmb_3_LMB_WriteDBus,
      LMB_AddrStrobe => dlmb_3_LMB_AddrStrobe,
      LMB_ReadStrobe => dlmb_3_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_3_LMB_WriteStrobe,
      LMB_BE => dlmb_3_LMB_BE,
      Sl_DBus => dlmb_3_Sl_DBus,
      Sl_Ready => dlmb_3_Sl_Ready(0),
      BRAM_Rst_A => dlmb_cntlr_3_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => dlmb_cntlr_3_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => dlmb_cntlr_3_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => dlmb_cntlr_3_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => dlmb_cntlr_3_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => dlmb_cntlr_3_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => dlmb_cntlr_3_BRAM_PORT_BRAM_Dout
    );

  dlmb_cntlr_2 : dlmb_cntlr_2_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => dlmb_2_OPB_Rst,
      LMB_ABus => dlmb_2_LMB_ABus,
      LMB_WriteDBus => dlmb_2_LMB_WriteDBus,
      LMB_AddrStrobe => dlmb_2_LMB_AddrStrobe,
      LMB_ReadStrobe => dlmb_2_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_2_LMB_WriteStrobe,
      LMB_BE => dlmb_2_LMB_BE,
      Sl_DBus => dlmb_2_Sl_DBus,
      Sl_Ready => dlmb_2_Sl_Ready(0),
      BRAM_Rst_A => dlmb_cntlr_2_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => dlmb_cntlr_2_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => dlmb_cntlr_2_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => dlmb_cntlr_2_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => dlmb_cntlr_2_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => dlmb_cntlr_2_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => dlmb_cntlr_2_BRAM_PORT_BRAM_Dout
    );

  dlmb_cntlr_1 : dlmb_cntlr_1_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => dlmb_1_OPB_Rst,
      LMB_ABus => dlmb_1_LMB_ABus,
      LMB_WriteDBus => dlmb_1_LMB_WriteDBus,
      LMB_AddrStrobe => dlmb_1_LMB_AddrStrobe,
      LMB_ReadStrobe => dlmb_1_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_1_LMB_WriteStrobe,
      LMB_BE => dlmb_1_LMB_BE,
      Sl_DBus => dlmb_1_Sl_DBus,
      Sl_Ready => dlmb_1_Sl_Ready(0),
      BRAM_Rst_A => dlmb_cntlr_1_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => dlmb_cntlr_1_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => dlmb_cntlr_1_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => dlmb_cntlr_1_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => dlmb_cntlr_1_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => dlmb_cntlr_1_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => dlmb_cntlr_1_BRAM_PORT_BRAM_Dout
    );

  dlmb_cntlr_0 : dlmb_cntlr_0_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      LMB_Rst => dlmb_0_OPB_Rst,
      LMB_ABus => dlmb_0_LMB_ABus,
      LMB_WriteDBus => dlmb_0_LMB_WriteDBus,
      LMB_AddrStrobe => dlmb_0_LMB_AddrStrobe,
      LMB_ReadStrobe => dlmb_0_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_0_LMB_WriteStrobe,
      LMB_BE => dlmb_0_LMB_BE,
      Sl_DBus => dlmb_0_Sl_DBus,
      Sl_Ready => dlmb_0_Sl_Ready(0),
      BRAM_Rst_A => dlmb_port_BRAM_Rst,
      BRAM_Clk_A => dlmb_port_BRAM_Clk,
      BRAM_EN_A => dlmb_port_BRAM_EN,
      BRAM_WEN_A => dlmb_port_BRAM_WEN,
      BRAM_Addr_A => dlmb_port_BRAM_Addr,
      BRAM_Din_A => dlmb_port_BRAM_Din,
      BRAM_Dout_A => dlmb_port_BRAM_Dout
    );

  dlmb_3 : dlmb_3_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => dlmb_3_OPB_Rst,
      M_ABus => dlmb_3_M_ABus,
      M_ReadStrobe => dlmb_3_M_ReadStrobe,
      M_WriteStrobe => dlmb_3_M_WriteStrobe,
      M_AddrStrobe => dlmb_3_M_AddrStrobe,
      M_DBus => dlmb_3_M_DBus,
      M_BE => dlmb_3_M_BE,
      Sl_DBus => dlmb_3_Sl_DBus,
      Sl_Ready => dlmb_3_Sl_Ready(0 to 0),
      LMB_ABus => dlmb_3_LMB_ABus,
      LMB_ReadStrobe => dlmb_3_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_3_LMB_WriteStrobe,
      LMB_AddrStrobe => dlmb_3_LMB_AddrStrobe,
      LMB_ReadDBus => dlmb_3_LMB_ReadDBus,
      LMB_WriteDBus => dlmb_3_LMB_WriteDBus,
      LMB_Ready => dlmb_3_LMB_Ready,
      LMB_BE => dlmb_3_LMB_BE
    );

  dlmb_2 : dlmb_2_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => dlmb_2_OPB_Rst,
      M_ABus => dlmb_2_M_ABus,
      M_ReadStrobe => dlmb_2_M_ReadStrobe,
      M_WriteStrobe => dlmb_2_M_WriteStrobe,
      M_AddrStrobe => dlmb_2_M_AddrStrobe,
      M_DBus => dlmb_2_M_DBus,
      M_BE => dlmb_2_M_BE,
      Sl_DBus => dlmb_2_Sl_DBus,
      Sl_Ready => dlmb_2_Sl_Ready(0 to 0),
      LMB_ABus => dlmb_2_LMB_ABus,
      LMB_ReadStrobe => dlmb_2_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_2_LMB_WriteStrobe,
      LMB_AddrStrobe => dlmb_2_LMB_AddrStrobe,
      LMB_ReadDBus => dlmb_2_LMB_ReadDBus,
      LMB_WriteDBus => dlmb_2_LMB_WriteDBus,
      LMB_Ready => dlmb_2_LMB_Ready,
      LMB_BE => dlmb_2_LMB_BE
    );

  dlmb_1 : dlmb_1_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => dlmb_1_OPB_Rst,
      M_ABus => dlmb_1_M_ABus,
      M_ReadStrobe => dlmb_1_M_ReadStrobe,
      M_WriteStrobe => dlmb_1_M_WriteStrobe,
      M_AddrStrobe => dlmb_1_M_AddrStrobe,
      M_DBus => dlmb_1_M_DBus,
      M_BE => dlmb_1_M_BE,
      Sl_DBus => dlmb_1_Sl_DBus,
      Sl_Ready => dlmb_1_Sl_Ready(0 to 0),
      LMB_ABus => dlmb_1_LMB_ABus,
      LMB_ReadStrobe => dlmb_1_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_1_LMB_WriteStrobe,
      LMB_AddrStrobe => dlmb_1_LMB_AddrStrobe,
      LMB_ReadDBus => dlmb_1_LMB_ReadDBus,
      LMB_WriteDBus => dlmb_1_LMB_WriteDBus,
      LMB_Ready => dlmb_1_LMB_Ready,
      LMB_BE => dlmb_1_LMB_BE
    );

  dlmb_0 : dlmb_0_wrapper
    port map (
      LMB_Clk => sys_clk_s,
      SYS_Rst => sys_rst_s,
      LMB_Rst => dlmb_0_OPB_Rst,
      M_ABus => dlmb_0_M_ABus,
      M_ReadStrobe => dlmb_0_M_ReadStrobe,
      M_WriteStrobe => dlmb_0_M_WriteStrobe,
      M_AddrStrobe => dlmb_0_M_AddrStrobe,
      M_DBus => dlmb_0_M_DBus,
      M_BE => dlmb_0_M_BE,
      Sl_DBus => dlmb_0_Sl_DBus,
      Sl_Ready => dlmb_0_Sl_Ready(0 to 0),
      LMB_ABus => dlmb_0_LMB_ABus,
      LMB_ReadStrobe => dlmb_0_LMB_ReadStrobe,
      LMB_WriteStrobe => dlmb_0_LMB_WriteStrobe,
      LMB_AddrStrobe => dlmb_0_LMB_AddrStrobe,
      LMB_ReadDBus => dlmb_0_LMB_ReadDBus,
      LMB_WriteDBus => dlmb_0_LMB_WriteDBus,
      LMB_Ready => dlmb_0_LMB_Ready,
      LMB_BE => dlmb_0_LMB_BE
    );

  debug_module : debug_module_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      Interrupt => open,
      Debug_SYS_Rst => P0_opb_Debug_SYS_Rst,
      Debug_Rst => Debug_Rst,
      Ext_BRK => Ext_BRK,
      Ext_NM_BRK => Ext_NM_BRK,
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      OPB_DBus => P0_opb_OPB_DBus,
      MDM_DBus => P0_opb_Sl_DBus(96 to 127),
      MDM_errAck => P0_opb_Sl_errAck(3),
      MDM_retry => P0_opb_Sl_retry(3),
      MDM_toutSup => P0_opb_Sl_toutSup(3),
      MDM_xferAck => P0_opb_Sl_xferAck(3),
      Dbg_Clk_0 => DBG_CLK_s,
      Dbg_TDI_0 => DBG_TDI_s,
      Dbg_TDO_0 => DBG_TDO_s,
      Dbg_Reg_En_0 => DBG_REG_EN_s,
      Dbg_Capture_0 => DBG_CAPTURE_s,
      Dbg_Update_0 => DBG_UPDATE_s,
      Dbg_Clk_1 => open,
      Dbg_TDI_1 => open,
      Dbg_TDO_1 => net_gnd0,
      Dbg_Reg_En_1 => open,
      Dbg_Capture_1 => open,
      Dbg_Update_1 => open,
      Dbg_Clk_2 => open,
      Dbg_TDI_2 => open,
      Dbg_TDO_2 => net_gnd0,
      Dbg_Reg_En_2 => open,
      Dbg_Capture_2 => open,
      Dbg_Update_2 => open,
      Dbg_Clk_3 => open,
      Dbg_TDI_3 => open,
      Dbg_TDO_3 => net_gnd0,
      Dbg_Reg_En_3 => open,
      Dbg_Capture_3 => open,
      Dbg_Update_3 => open,
      Dbg_Clk_4 => open,
      Dbg_TDI_4 => open,
      Dbg_TDO_4 => net_gnd0,
      Dbg_Reg_En_4 => open,
      Dbg_Capture_4 => open,
      Dbg_Update_4 => open,
      Dbg_Clk_5 => open,
      Dbg_TDI_5 => open,
      Dbg_TDO_5 => net_gnd0,
      Dbg_Reg_En_5 => open,
      Dbg_Capture_5 => open,
      Dbg_Update_5 => open,
      Dbg_Clk_6 => open,
      Dbg_TDI_6 => open,
      Dbg_TDO_6 => net_gnd0,
      Dbg_Reg_En_6 => open,
      Dbg_Capture_6 => open,
      Dbg_Update_6 => open,
      Dbg_Clk_7 => open,
      Dbg_TDI_7 => open,
      Dbg_TDO_7 => net_gnd0,
      Dbg_Reg_En_7 => open,
      Dbg_Capture_7 => open,
      Dbg_Update_7 => open,
      bscan_tdi => open,
      bscan_reset => open,
      bscan_shift => open,
      bscan_update => open,
      bscan_capture => open,
      bscan_sel1 => open,
      bscan_drck1 => open,
      bscan_tdo1 => net_gnd0,
      FSL0_S_CLK => open,
      FSL0_S_READ => open,
      FSL0_S_DATA => net_gnd32,
      FSL0_S_CONTROL => net_gnd0,
      FSL0_S_EXISTS => net_gnd0,
      FSL0_M_CLK => open,
      FSL0_M_WRITE => open,
      FSL0_M_DATA => open,
      FSL0_M_CONTROL => open,
      FSL0_M_FULL => net_gnd0
    );

  dcm_0 : dcm_0_wrapper
    port map (
      RST => net_gnd0,
      CLKIN => dcm_clk_s,
      CLKFB => sys_clk_s,
      PSEN => net_gnd0,
      PSINCDEC => net_gnd0,
      PSCLK => net_gnd0,
      DSSEN => net_gnd0,
      CLK0 => sys_clk_s,
      CLK90 => open,
      CLK180 => open,
      CLK270 => open,
      CLKDV => open,
      CLK2X => open,
      CLK2X180 => open,
      CLKFX => open,
      CLKFX180 => open,
      STATUS => open,
      LOCKED => open,
      PSDONE => open
    );

  bram_block_3 : bram_block_3_wrapper
    port map (
      BRAM_Rst_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_3_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_3_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_3_BRAM_PORT_BRAM_Dout,
      BRAM_Rst_B => dlmb_cntlr_3_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_B => dlmb_cntlr_3_BRAM_PORT_BRAM_Clk,
      BRAM_EN_B => dlmb_cntlr_3_BRAM_PORT_BRAM_EN,
      BRAM_WEN_B => dlmb_cntlr_3_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_B => dlmb_cntlr_3_BRAM_PORT_BRAM_Addr,
      BRAM_Din_B => dlmb_cntlr_3_BRAM_PORT_BRAM_Din,
      BRAM_Dout_B => dlmb_cntlr_3_BRAM_PORT_BRAM_Dout
    );

  bram_block_2 : bram_block_2_wrapper
    port map (
      BRAM_Rst_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_2_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_2_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_2_BRAM_PORT_BRAM_Dout,
      BRAM_Rst_B => dlmb_cntlr_2_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_B => dlmb_cntlr_2_BRAM_PORT_BRAM_Clk,
      BRAM_EN_B => dlmb_cntlr_2_BRAM_PORT_BRAM_EN,
      BRAM_WEN_B => dlmb_cntlr_2_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_B => dlmb_cntlr_2_BRAM_PORT_BRAM_Addr,
      BRAM_Din_B => dlmb_cntlr_2_BRAM_PORT_BRAM_Din,
      BRAM_Dout_B => dlmb_cntlr_2_BRAM_PORT_BRAM_Dout
    );

  bram_block_1 : bram_block_1_wrapper
    port map (
      BRAM_Rst_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Clk,
      BRAM_EN_A => ilmb_cntlr_1_BRAM_PORT_BRAM_EN,
      BRAM_WEN_A => ilmb_cntlr_1_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Addr,
      BRAM_Din_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Din,
      BRAM_Dout_A => ilmb_cntlr_1_BRAM_PORT_BRAM_Dout,
      BRAM_Rst_B => dlmb_cntlr_1_BRAM_PORT_BRAM_Rst,
      BRAM_Clk_B => dlmb_cntlr_1_BRAM_PORT_BRAM_Clk,
      BRAM_EN_B => dlmb_cntlr_1_BRAM_PORT_BRAM_EN,
      BRAM_WEN_B => dlmb_cntlr_1_BRAM_PORT_BRAM_WEN,
      BRAM_Addr_B => dlmb_cntlr_1_BRAM_PORT_BRAM_Addr,
      BRAM_Din_B => dlmb_cntlr_1_BRAM_PORT_BRAM_Din,
      BRAM_Dout_B => dlmb_cntlr_1_BRAM_PORT_BRAM_Dout
    );

  RS232_Uart_1 : rs232_uart_1_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      Interrupt => open,
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      OPB_DBus => P0_opb_OPB_DBus,
      UART_DBus => P0_opb_Sl_DBus(128 to 159),
      UART_errAck => P0_opb_Sl_errAck(4),
      UART_retry => P0_opb_Sl_retry(4),
      UART_toutSup => P0_opb_Sl_toutSup(4),
      UART_xferAck => P0_opb_Sl_xferAck(4),
      RX => fpga_0_RS232_Uart_1_RX,
      TX => fpga_0_RS232_Uart_1_TX
    );

  PushButtons_5Bit : pushbuttons_5bit_wrapper
    port map (
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_Clk => sys_clk_s,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_Rst => P0_opb_OPB_Rst,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      Sln_DBus => P0_opb_Sl_DBus(160 to 191),
      Sln_errAck => P0_opb_Sl_errAck(5),
      Sln_retry => P0_opb_Sl_retry(5),
      Sln_toutSup => P0_opb_Sl_toutSup(5),
      Sln_xferAck => P0_opb_Sl_xferAck(5),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd5,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd5,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_PushButtons_5Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_PushButtons_5Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_PushButtons_5Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd5,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  P3_opb : p3_opb_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P3_opb_OPB_Rst,
      SYS_Rst => sys_rst_s,
      Debug_SYS_Rst => net_gnd0,
      WDT_Rst => net_gnd0,
      M_ABus => P3_opb_M_ABus,
      M_BE => P3_opb_M_BE,
      M_beXfer => net_gnd2,
      M_busLock => P3_opb_M_busLock,
      M_DBus => P3_opb_M_DBus,
      M_DBusEn => net_gnd2,
      M_DBusEn32_63 => net_vcc2,
      M_dwXfer => net_gnd2,
      M_fwXfer => net_gnd2,
      M_hwXfer => net_gnd2,
      M_request => P3_opb_M_request,
      M_RNW => P3_opb_M_RNW,
      M_select => P3_opb_M_select,
      M_seqAddr => P3_opb_M_seqAddr,
      Sl_beAck => net_gnd2,
      Sl_DBus => P3_opb_Sl_DBus,
      Sl_DBusEn => net_vcc2,
      Sl_DBusEn32_63 => net_vcc2,
      Sl_errAck => P3_opb_Sl_errAck,
      Sl_dwAck => net_gnd2,
      Sl_fwAck => net_gnd2,
      Sl_hwAck => net_gnd2,
      Sl_retry => P3_opb_Sl_retry,
      Sl_toutSup => P3_opb_Sl_toutSup,
      Sl_xferAck => P3_opb_Sl_xferAck,
      OPB_MRequest => open,
      OPB_ABus => P3_opb_OPB_ABus,
      OPB_BE => P3_opb_OPB_BE,
      OPB_beXfer => open,
      OPB_beAck => open,
      OPB_busLock => open,
      OPB_rdDBus => open,
      OPB_wrDBus => open,
      OPB_DBus => P3_opb_OPB_DBus,
      OPB_errAck => P3_opb_OPB_errAck,
      OPB_dwAck => open,
      OPB_dwXfer => open,
      OPB_fwAck => open,
      OPB_fwXfer => open,
      OPB_hwAck => open,
      OPB_hwXfer => open,
      OPB_MGrant => P3_opb_OPB_MGrant,
      OPB_pendReq => open,
      OPB_retry => P3_opb_OPB_retry,
      OPB_RNW => P3_opb_OPB_RNW,
      OPB_select => P3_opb_OPB_select,
      OPB_seqAddr => P3_opb_OPB_seqAddr,
      OPB_timeout => P3_opb_OPB_timeout,
      OPB_toutSup => open,
      OPB_xferAck => P3_opb_OPB_xferAck
    );

  P2_opb : p2_opb_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P2_opb_OPB_Rst,
      SYS_Rst => sys_rst_s,
      Debug_SYS_Rst => net_gnd0,
      WDT_Rst => net_gnd0,
      M_ABus => P2_opb_M_ABus,
      M_BE => P2_opb_M_BE,
      M_beXfer => net_gnd2,
      M_busLock => P2_opb_M_busLock,
      M_DBus => P2_opb_M_DBus,
      M_DBusEn => net_gnd2,
      M_DBusEn32_63 => net_vcc2,
      M_dwXfer => net_gnd2,
      M_fwXfer => net_gnd2,
      M_hwXfer => net_gnd2,
      M_request => P2_opb_M_request,
      M_RNW => P2_opb_M_RNW,
      M_select => P2_opb_M_select,
      M_seqAddr => P2_opb_M_seqAddr,
      Sl_beAck => net_gnd2,
      Sl_DBus => P2_opb_Sl_DBus,
      Sl_DBusEn => net_vcc2,
      Sl_DBusEn32_63 => net_vcc2,
      Sl_errAck => P2_opb_Sl_errAck,
      Sl_dwAck => net_gnd2,
      Sl_fwAck => net_gnd2,
      Sl_hwAck => net_gnd2,
      Sl_retry => P2_opb_Sl_retry,
      Sl_toutSup => P2_opb_Sl_toutSup,
      Sl_xferAck => P2_opb_Sl_xferAck,
      OPB_MRequest => open,
      OPB_ABus => P2_opb_OPB_ABus,
      OPB_BE => P2_opb_OPB_BE,
      OPB_beXfer => open,
      OPB_beAck => open,
      OPB_busLock => open,
      OPB_rdDBus => open,
      OPB_wrDBus => open,
      OPB_DBus => P2_opb_OPB_DBus,
      OPB_errAck => P2_opb_OPB_errAck,
      OPB_dwAck => open,
      OPB_dwXfer => open,
      OPB_fwAck => open,
      OPB_fwXfer => open,
      OPB_hwAck => open,
      OPB_hwXfer => open,
      OPB_MGrant => P2_opb_OPB_MGrant,
      OPB_pendReq => open,
      OPB_retry => P2_opb_OPB_retry,
      OPB_RNW => P2_opb_OPB_RNW,
      OPB_select => P2_opb_OPB_select,
      OPB_seqAddr => P2_opb_OPB_seqAddr,
      OPB_timeout => P2_opb_OPB_timeout,
      OPB_toutSup => open,
      OPB_xferAck => P2_opb_OPB_xferAck
    );

  P1_opb : p1_opb_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P1_opb_OPB_Rst,
      SYS_Rst => sys_rst_s,
      Debug_SYS_Rst => net_gnd0,
      WDT_Rst => net_gnd0,
      M_ABus => P1_opb_M_ABus,
      M_BE => P1_opb_M_BE,
      M_beXfer => net_gnd2,
      M_busLock => P1_opb_M_busLock,
      M_DBus => P1_opb_M_DBus,
      M_DBusEn => net_gnd2,
      M_DBusEn32_63 => net_vcc2,
      M_dwXfer => net_gnd2,
      M_fwXfer => net_gnd2,
      M_hwXfer => net_gnd2,
      M_request => P1_opb_M_request,
      M_RNW => P1_opb_M_RNW,
      M_select => P1_opb_M_select,
      M_seqAddr => P1_opb_M_seqAddr,
      Sl_beAck => net_gnd2,
      Sl_DBus => P1_opb_Sl_DBus,
      Sl_DBusEn => net_vcc2,
      Sl_DBusEn32_63 => net_vcc2,
      Sl_errAck => P1_opb_Sl_errAck,
      Sl_dwAck => net_gnd2,
      Sl_fwAck => net_gnd2,
      Sl_hwAck => net_gnd2,
      Sl_retry => P1_opb_Sl_retry,
      Sl_toutSup => P1_opb_Sl_toutSup,
      Sl_xferAck => P1_opb_Sl_xferAck,
      OPB_MRequest => open,
      OPB_ABus => P1_opb_OPB_ABus,
      OPB_BE => P1_opb_OPB_BE,
      OPB_beXfer => open,
      OPB_beAck => open,
      OPB_busLock => open,
      OPB_rdDBus => open,
      OPB_wrDBus => open,
      OPB_DBus => P1_opb_OPB_DBus,
      OPB_errAck => P1_opb_OPB_errAck,
      OPB_dwAck => open,
      OPB_dwXfer => open,
      OPB_fwAck => open,
      OPB_fwXfer => open,
      OPB_hwAck => open,
      OPB_hwXfer => open,
      OPB_MGrant => P1_opb_OPB_MGrant,
      OPB_pendReq => open,
      OPB_retry => P1_opb_OPB_retry,
      OPB_RNW => P1_opb_OPB_RNW,
      OPB_select => P1_opb_OPB_select,
      OPB_seqAddr => P1_opb_OPB_seqAddr,
      OPB_timeout => P1_opb_OPB_timeout,
      OPB_toutSup => open,
      OPB_xferAck => P1_opb_OPB_xferAck
    );

  P0_opb : p0_opb_wrapper
    port map (
      OPB_Clk => sys_clk_s,
      OPB_Rst => P0_opb_OPB_Rst,
      SYS_Rst => sys_rst_s,
      Debug_SYS_Rst => P0_opb_Debug_SYS_Rst,
      WDT_Rst => net_gnd0,
      M_ABus => P0_opb_M_ABus,
      M_BE => P0_opb_M_BE,
      M_beXfer => net_gnd2,
      M_busLock => P0_opb_M_busLock,
      M_DBus => P0_opb_M_DBus,
      M_DBusEn => net_gnd2,
      M_DBusEn32_63 => net_vcc2,
      M_dwXfer => net_gnd2,
      M_fwXfer => net_gnd2,
      M_hwXfer => net_gnd2,
      M_request => P0_opb_M_request,
      M_RNW => P0_opb_M_RNW,
      M_select => P0_opb_M_select,
      M_seqAddr => P0_opb_M_seqAddr,
      Sl_beAck => net_gnd8,
      Sl_DBus => P0_opb_Sl_DBus,
      Sl_DBusEn => net_vcc8,
      Sl_DBusEn32_63 => net_vcc8,
      Sl_errAck => P0_opb_Sl_errAck,
      Sl_dwAck => net_gnd8,
      Sl_fwAck => net_gnd8,
      Sl_hwAck => net_gnd8,
      Sl_retry => P0_opb_Sl_retry,
      Sl_toutSup => P0_opb_Sl_toutSup,
      Sl_xferAck => P0_opb_Sl_xferAck,
      OPB_MRequest => open,
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_beXfer => open,
      OPB_beAck => open,
      OPB_busLock => open,
      OPB_rdDBus => open,
      OPB_wrDBus => open,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_errAck => P0_opb_OPB_errAck,
      OPB_dwAck => open,
      OPB_dwXfer => open,
      OPB_fwAck => open,
      OPB_fwXfer => open,
      OPB_hwAck => open,
      OPB_hwXfer => open,
      OPB_MGrant => P0_opb_OPB_MGrant,
      OPB_pendReq => open,
      OPB_retry => P0_opb_OPB_retry,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      OPB_timeout => P0_opb_OPB_timeout,
      OPB_toutSup => open,
      OPB_xferAck => P0_opb_OPB_xferAck
    );

  LEDs_4Bit : leds_4bit_wrapper
    port map (
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_Clk => sys_clk_s,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_Rst => P0_opb_OPB_Rst,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      Sln_DBus => P0_opb_Sl_DBus(192 to 223),
      Sln_errAck => P0_opb_Sl_errAck(6),
      Sln_retry => P0_opb_Sl_retry(6),
      Sln_toutSup => P0_opb_Sl_toutSup(6),
      Sln_xferAck => P0_opb_Sl_xferAck(6),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd4,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd4,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_LEDs_4Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_LEDs_4Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_LEDs_4Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd4,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  DIPSWs_4Bit : dipsws_4bit_wrapper
    port map (
      OPB_ABus => P0_opb_OPB_ABus,
      OPB_BE => P0_opb_OPB_BE,
      OPB_Clk => sys_clk_s,
      OPB_DBus => P0_opb_OPB_DBus,
      OPB_RNW => P0_opb_OPB_RNW,
      OPB_Rst => P0_opb_OPB_Rst,
      OPB_select => P0_opb_OPB_select,
      OPB_seqAddr => P0_opb_OPB_seqAddr,
      Sln_DBus => P0_opb_Sl_DBus(224 to 255),
      Sln_errAck => P0_opb_Sl_errAck(7),
      Sln_retry => P0_opb_Sl_retry(7),
      Sln_toutSup => P0_opb_Sl_toutSup(7),
      Sln_xferAck => P0_opb_Sl_xferAck(7),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd4,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd4,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_DIPSWs_4Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_DIPSWs_4Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_DIPSWs_4Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd4,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  iobuf_0 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(0),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(0),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(0),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(0)
    );

  iobuf_1 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(1),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(1),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(1),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(1)
    );

  iobuf_2 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(2),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(2),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(2),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(2)
    );

  iobuf_3 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(3),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(3),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(3),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(3)
    );

  iobuf_4 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(0),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(0),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(0),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(0)
    );

  iobuf_5 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(1),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(1),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(1),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(1)
    );

  iobuf_6 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(2),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(2),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(2),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(2)
    );

  iobuf_7 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(3),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(3),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(3),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(3)
    );

  iobuf_8 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(0),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(0),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(0),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(0)
    );

  iobuf_9 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(1),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(1),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(1),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(1)
    );

  iobuf_10 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(2),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(2),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(2),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(2)
    );

  iobuf_11 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(3),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(3),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(3),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(3)
    );

  iobuf_12 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(4),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(4),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(4),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(4)
    );

end architecture STRUCTURE;

