-------------------------------------------------------------------------------
-- shared_mem_if_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library shared_mem_if_v1_00_a;
use shared_mem_if_v1_00_a.all;

entity shared_mem_if_1_wrapper is
  port (
    External_Mem_Addr : out std_logic_vector(12 downto 0);
    External_Mem_Data_Out : out std_logic_vector(15 downto 0);
    External_Mem_Data_In : in std_logic_vector(15 downto 0);
    External_Mem_RD_WR : out std_logic;
    External_Mem_Request : out std_logic;
    External_Mem_Ack_out : out std_logic;
    External_Mem_Ack_in : in std_logic;
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;
    Sl_DBus : out std_logic_vector(0 to 31);
    Sl_errAck : out std_logic;
    Sl_retry : out std_logic;
    Sl_toutSup : out std_logic;
    Sl_xferAck : out std_logic;
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_BE : in std_logic_vector(0 to 3);
    OPB_DBus : in std_logic_vector(0 to 31);
    OPB_RNW : in std_logic;
    OPB_select : in std_logic;
    OPB_seqAddr : in std_logic
  );

  attribute x_core_info : STRING;
  attribute x_core_info of shared_mem_if_1_wrapper : entity is "shared_mem_if_v1_00_a";

end shared_mem_if_1_wrapper;

architecture STRUCTURE of shared_mem_if_1_wrapper is

  component shared_mem_if is
    generic (
      USER_EXT_ADDR_WIDTH : INTEGER;
      USER_EXT_DATA_WIDTH : INTEGER;
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_DWIDTH : INTEGER;
      C_USER_ID_CODE : INTEGER;
      C_FAMILY : STRING
    );
    port (
      External_Mem_Addr : out std_logic_vector((USER_EXT_ADDR_WIDTH-1) downto 0);
      External_Mem_Data_Out : out std_logic_vector((USER_EXT_DATA_WIDTH-1) downto 0);
      External_Mem_Data_In : in std_logic_vector((USER_EXT_DATA_WIDTH-1) downto 0);
      External_Mem_RD_WR : out std_logic;
      External_Mem_Request : out std_logic;
      External_Mem_Ack_out : out std_logic;
      External_Mem_Ack_in : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_BE : in std_logic_vector(0 to ((C_OPB_DWIDTH/8)-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

begin

  shared_mem_if_1 : shared_mem_if
    generic map (
      USER_EXT_ADDR_WIDTH => 13,
      USER_EXT_DATA_WIDTH => 16,
      C_BASEADDR => X"7fe00000",
      C_HIGHADDR => X"7fe0ffff",
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32,
      C_USER_ID_CODE => 3,
      C_FAMILY => "virtex2p"
    )
    port map (
      External_Mem_Addr => External_Mem_Addr,
      External_Mem_Data_Out => External_Mem_Data_Out,
      External_Mem_Data_In => External_Mem_Data_In,
      External_Mem_RD_WR => External_Mem_RD_WR,
      External_Mem_Request => External_Mem_Request,
      External_Mem_Ack_out => External_Mem_Ack_out,
      External_Mem_Ack_in => External_Mem_Ack_in,
      OPB_Clk => OPB_Clk,
      OPB_Rst => OPB_Rst,
      Sl_DBus => Sl_DBus,
      Sl_errAck => Sl_errAck,
      Sl_retry => Sl_retry,
      Sl_toutSup => Sl_toutSup,
      Sl_xferAck => Sl_xferAck,
      OPB_ABus => OPB_ABus,
      OPB_BE => OPB_BE,
      OPB_DBus => OPB_DBus,
      OPB_RNW => OPB_RNW,
      OPB_select => OPB_select,
      OPB_seqAddr => OPB_seqAddr
    );

end architecture STRUCTURE;

