EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
0 GLB | Ext_Pin_0 | I | 1 | net_ExternalPort_0 |
1 GLB | Ext_Pin_1 | I | 1 | net_ExternalPort_0 |
2 A | fpga_0_DIPSWs_4Bit_GPIO_IO_pin | IO | 0:3 | fpga_0_DIPSWs_4Bit_GPIO_IO |
3 B | LEDs_4Bit_GPIO_in_pin | I | 0:3 | LEDs_4Bit_GPIO_in |
4 B | fpga_0_LEDs_4Bit_GPIO_IO_pin | IO | 0:3 | fpga_0_LEDs_4Bit_GPIO_IO |
5 C | fpga_0_PushButtons_5Bit_GPIO_IO_pin | IO | 0:4 | fpga_0_PushButtons_5Bit_GPIO_IO |
6 D | sys_clk_pin | I | 1 | dcm_clk_s | CLK
7 D | fpga_0_net_gnd_1_pin | O | 1 | net_gnd |
8 D | fpga_0_net_gnd_2_pin | O | 1 | net_gnd |
9 D | fpga_0_net_gnd_3_pin | O | 1 | net_gnd |
10 D | fpga_0_net_gnd_4_pin | O | 1 | net_gnd |
11 D | fpga_0_net_gnd_5_pin | O | 1 | net_gnd |
12 D | fpga_0_net_gnd_6_pin | O | 1 | net_gnd |
13 D | fpga_0_net_gnd_pin | O | 1 | net_gnd |
14 E | sys_rst_pin | I | 1 | sys_rst_s | RESET