----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:46:33 04/15/2009 
-- Design Name: 
-- Module Name:    clk_divide - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_divide is
	Generic
	(
		DIV_FACTOR : integer := 10
	);	
	Port 
	( 
		clk_in : in  STD_LOGIC;
      clk_out : out  STD_LOGIC;
      reset : in  STD_LOGIC
	);
end clk_divide;

architecture Behavioral of clk_divide is
	signal clk_state : std_logic := '1';

begin
	clk_out <= clk_state;
	
	div_process : process( clk_in ) is
	variable count : integer := 0;
		
	begin	
		if (clk_in'event and clk_in = '1') then
			if (reset = '1') then
				count := 0;				
				clk_state <= '1';
			else
				count := count + 1;
				
				if (count >= DIV_FACTOR) then
					count := 0;
					clk_state <= not clk_state;
				end if;
				
			end if;
		end if;
	end process div_process;

end Behavioral;

