-------------------------------------------------------------------------------
-- task_controller_if_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library task_controller_if_v1_00_a;
use task_controller_if_v1_00_a.all;

entity task_controller_if_1_wrapper is
  port (
    start_task_control : out std_logic;
    executing : out std_logic;
    iteration_num : in std_logic_vector(15 downto 0);
    start_exec : in std_logic;
    dfg_node : in std_logic_vector(7 downto 0);
    proc_done : in std_logic;
    all_procs_done : in std_logic;
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;
    Sl_DBus : out std_logic_vector(0 to 31);
    Sl_errAck : out std_logic;
    Sl_retry : out std_logic;
    Sl_toutSup : out std_logic;
    Sl_xferAck : out std_logic;
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_BE : in std_logic_vector(0 to 3);
    OPB_DBus : in std_logic_vector(0 to 31);
    OPB_RNW : in std_logic;
    OPB_select : in std_logic;
    OPB_seqAddr : in std_logic
  );

  attribute x_core_info : STRING;
  attribute x_core_info of task_controller_if_1_wrapper : entity is "task_controller_if_v1_00_a";

end task_controller_if_1_wrapper;

architecture STRUCTURE of task_controller_if_1_wrapper is

  component task_controller_if is
    generic (
      ITER_NUM_WIDTH : INTEGER;
      DFG_NODE_WIDTH : INTEGER;
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_DWIDTH : INTEGER;
      C_USER_ID_CODE : INTEGER;
      C_FAMILY : STRING
    );
    port (
      start_task_control : out std_logic;
      executing : out std_logic;
      iteration_num : in std_logic_vector((ITER_NUM_WIDTH-1) downto 0);
      start_exec : in std_logic;
      dfg_node : in std_logic_vector((DFG_NODE_WIDTH-1) downto 0);
      proc_done : in std_logic;
      all_procs_done : in std_logic;
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_BE : in std_logic_vector(0 to ((C_OPB_DWIDTH/8)-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

begin

  task_controller_if_1 : task_controller_if
    generic map (
      ITER_NUM_WIDTH => 16,
      DFG_NODE_WIDTH => 8,
      C_BASEADDR => X"72400000",
      C_HIGHADDR => X"7240ffff",
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32,
      C_USER_ID_CODE => 3,
      C_FAMILY => "virtex2p"
    )
    port map (
      start_task_control => start_task_control,
      executing => executing,
      iteration_num => iteration_num,
      start_exec => start_exec,
      dfg_node => dfg_node,
      proc_done => proc_done,
      all_procs_done => all_procs_done,
      OPB_Clk => OPB_Clk,
      OPB_Rst => OPB_Rst,
      Sl_DBus => Sl_DBus,
      Sl_errAck => Sl_errAck,
      Sl_retry => Sl_retry,
      Sl_toutSup => Sl_toutSup,
      Sl_xferAck => Sl_xferAck,
      OPB_ABus => OPB_ABus,
      OPB_BE => OPB_BE,
      OPB_DBus => OPB_DBus,
      OPB_RNW => OPB_RNW,
      OPB_select => OPB_select,
      OPB_seqAddr => OPB_seqAddr
    );

end architecture STRUCTURE;

