--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.1i
--  \   \         Application : ISE
--  /   /         Filename : mem_cntrl_tb_selfcheck.vhw
-- /___/   /\     Timestamp : Sat Mar 21 19:48:23 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: mem_cntrl_tb_selfcheck_beh
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY mem_cntrl_tb_selfcheck_beh IS
END mem_cntrl_tb_selfcheck_beh;

ARCHITECTURE testbench_arch OF mem_cntrl_tb_selfcheck_beh IS
    COMPONENT memory_controller
        PORT (
            clk : In std_logic;
            reset : In std_logic;
            micro_addr_buses : In std_logic_vector (63 DownTo 0);
            micro_data_buses : InOut std_logic_vector (63 DownTo 0);
            micro_mem_requests : In std_logic_vector (1 DownTo 0);
            micro_ack_ins : In std_logic_vector (1 DownTo 0);
            micro_ack_outs : Out std_logic_vector (1 DownTo 0);
            micro_read_write : In std_logic_vector (1 DownTo 0);
            mem_addr : Out std_logic_vector (31 DownTo 0);
            mem_data : InOut std_logic_vector (31 DownTo 0);
            mem_read_write : Out std_logic;
            mem_CE : Out std_logic
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL micro_addr_buses : std_logic_vector (63 DownTo 0) := "0000000000000000000000000000000000000000000000000000000000000000";
    SIGNAL micro_data_buses : std_logic_vector (63 DownTo 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    SIGNAL micro_mem_requests : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL micro_ack_ins : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL micro_ack_outs : std_logic_vector (1 DownTo 0) := "UU";
    SIGNAL micro_read_write : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL mem_addr : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
    SIGNAL mem_data : std_logic_vector (31 DownTo 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    SIGNAL mem_read_write : std_logic := 'U';
    SIGNAL mem_CE : std_logic := 'U';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 100 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : memory_controller
        PORT MAP (
            clk => clk,
            reset => reset,
            micro_addr_buses => micro_addr_buses,
            micro_data_buses => micro_data_buses,
            micro_mem_requests => micro_mem_requests,
            micro_ack_ins => micro_ack_ins,
            micro_ack_outs => micro_ack_outs,
            micro_read_write => micro_read_write,
            mem_addr => mem_addr,
            mem_data => mem_data,
            mem_read_write => mem_read_write,
            mem_CE => mem_CE
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_mem_CE(
                next_mem_CE : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (mem_CE /= next_mem_CE) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns mem_CE="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mem_CE);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mem_CE);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_mem_addr(
                next_mem_addr : std_logic_vector (31 DownTo 0);
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (mem_addr /= next_mem_addr) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns mem_addr="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mem_addr);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mem_addr);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_mem_read_write(
                next_mem_read_write : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (mem_read_write /= next_mem_read_write) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns mem_read_write="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, mem_read_write);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_mem_read_write);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_micro_ack_outs(
                next_micro_ack_outs : std_logic_vector (1 DownTo 0);
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (micro_ack_outs /= next_micro_ack_outs) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns micro_ack_outs="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, micro_ack_outs);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_micro_ack_outs);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            BEGIN
                -- -------------  Current Time:  65ns
                WAIT FOR 65 ns;
                CHECK_mem_read_write('0', 65);
                CHECK_mem_CE('0', 65);
                -- -------------------------------------
                -- -------------  Current Time:  135ns
                WAIT FOR 70 ns;
                reset <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  235ns
                WAIT FOR 100 ns;
                micro_addr_buses <= "1010101010101010101010101010101001010101010101010101010101010101";
                micro_data_buses <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ00100011001000110010001100100011";
                micro_mem_requests <= "11";
                micro_read_write <= "11";
                -- -------------------------------------
                -- -------------  Current Time:  265ns
                WAIT FOR 30 ns;
                CHECK_mem_addr("01010101010101010101010101010101", 265);
                -- -------------------------------------
                WAIT FOR 835 ns;

                IF (TX_ERROR = 0) THEN
                    STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
                    ASSERT (FALSE) REPORT
                      "Simulation successful (not a failure).  No problems detected."
                      SEVERITY FAILURE;
                ELSE
                    STD.TEXTIO.write(TX_OUT, TX_ERROR);
                    STD.TEXTIO.write(TX_OUT,
                        string'(" errors found in simulation"));
                    ASSERT (FALSE) REPORT "Errors found during simulation"
                         SEVERITY FAILURE;
                END IF;
            END PROCESS;

    END testbench_arch;

