Unification of double-delay and SOC electromagnetic deembedding

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dc.contributor.authorRautio, JC
dc.contributor.authorOkhmatovski, VI
dc.date.accessioned2007-10-10T18:25:10Z
dc.date.available2007-10-10T18:25:10Z
dc.date.issued2005-09-30
dc.description.abstractDouble-delay and short open calibration (SOC) deembedding are both useful for deembedding the results of a gap voltage source excited electromagnetic analysis. Previously, each approach has been viewed as distinct, each with its own advantages and disadvantages. This paper describes a unifying theory, showing that double delay and SOC are each special cases of an extended SOC technique. Results related to the characteristic impedance as determined by this extended SOC deembedding are also presented.en
dc.format.extent309675 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citation0018-9480; IEEE TRANS MICROWAVE THEORY, SEP 2005, vol. 53, no. 9, p.2892 to 2898.en
dc.identifier.doihttp://dx.doi.org/10.1109/TMTT.2005.854250
dc.identifier.urihttp://hdl.handle.net/1993/2932
dc.language.isoengen_US
dc.rights©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en
dc.rightsrestricted accessen_US
dc.statusPeer revieweden
dc.subjectcalibrationen
dc.subjectcharacteristic impedanceen
dc.subjectdeembeddingen
dc.subjectelectromagnetic (EM) analysisen
dc.subjectmethod of moments (MoM)en
dc.subjectREVISITING CHARACTERISTIC IMPEDANCEen
dc.subjectWAVE CAD MODELSen
dc.subject3-D MOM SCHEMEen
dc.subjectPORT DISCONTINUITIESen
dc.subjectMULTIPORT CIRCUITSen
dc.subjectMICROSTRIP LINEen
dc.subjectDEFINITIONen
dc.subjectMOMENTSen
dc.subjectPLANEen
dc.titleUnification of double-delay and SOC electromagnetic deembeddingen
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